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TLV320AIC3104-Q1 Datasheet(PDF) 7 Page - Texas Instruments |
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TLV320AIC3104-Q1 Datasheet(HTML) 7 Page - Texas Instruments |
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7 / 95 page  7 TLV320AIC3104-Q1 www.ti.com SLAS715A – JUNE 2010 – REVISED MARCH 2016 Product Folder Links: TLV320AIC3104-Q1 Submit Documentation Feedback Copyright © 2010–2016, Texas Instruments Incorporated Electrical Characteristics (continued) At 25°C, AVDD_DAC = DRVDD = IOVDD = 3.3 V, DVDD = 1.8 V, fS = 48 kHz, 16-bit audio data (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT (3) Unless otherwise noted, all measurements use output common-mode voltage setting of 1.35 V, 0-dB output level control gain, 16- Ω single-ended load. Input resistance MIC1L/MIC1R inputs routed to single ADC input mix attenuation = 0 dB 20 k Ω MIC1L/MIC1R inputs routed to single ADC input mix attenuation = 12 dB 80 MIC2L/MIC2R inputs routed to single ADC input mix attenuation = 0 dB 20 MIC2L/MIC2R inputs routed to single ADC input mix attenuation = 12 dB 80 Input resistance 80 k Ω Input capacitance MIC1/LINE1 inputs 10 pF Input level control minimum attenuation setting 0 dB Input level control maximum attenuation setting 12 dB Input level control attenuation step size 1.5 dB ANALOG PASSTHROUGH MODE RDS(on) Input-to-output switch resistance MIC1/LIN1 to LINEOUT 330 Ω MIC2/LIN2 to LINEOUT 330 INPUT SIGNAL LEVEL, DIFFERENTIAL SNR Signal-to-noise ratio A-weighted, fS = 48 ksps, 0-dB PGA gain, inputs AC ‑shorted to ground 92 dB THD Total harmonic distortion fS = 48 kHz; 0-dB PGA gain, 1 kHz, –2-dB full-scale input signal –94 dB ADC DIGITAL DECIMATION FILTER, fS = 48 kHz Filter gain From 0 to 0.39 fS ±0.1 dB At 0.4125 fS –0.25 At 0.45 fS –3 At 0.5 fS –17.5 From 0.55 fS to 64 fS –75 Filter group delay 17/fS s MICROPHONE BIAS Bias voltage Programmable setting = 2 V 2 V Programmable setting = 2.5 V 2.3 2.455 2.7 Programmable setting = DRVDD DRVDD - 0.24 Current sourcing Programmable setting = 2.5 V 4 mA AUDIO DAC - DIFFERENTIAL LINE OUTPUT, RLOAD = 10 kΩ Full-scale output voltage 0-dB input full-scale signal, output common-mode setting = 1.35 V, output volume control = 0 dB 1.414 VRMS 4 VPP Signal-to-noise ratio(3) A-weighted, fS = 48 kHz, output volume control = 0 dB, no input signal, referenced to full-scale input level 90 102 dB Dynamic range A-weighted, fS = 48 kHz, –60-dB input full-scale signal, output volume control = 0 dB, output common-mode setting = 1.35 V 97 dB Total harmonic distortion fS = 48 kHz; 0-dB, 1-kHz input full-scale signal; output volume control = 0 dB; output common-mode setting = 1.35 V –95 –75 dB PSRR Power-supply rejection ratio 217-Hz signal applied to DRVDD, AVDD_DAC 78 dB 1-kHz signal applied to DRVDD, AVDD_DAC 80 DAC channel separation 0-dB full-scale input signal between left and right lineout 86 dB DAC interchannel gain mismatch 1-kHz input, 0-dB gain 0.1 dB DAC gain error 0-dB, 1-kHz input full-scale signal; output volume control = 0 dB; output common-mode setting = 1.35 V; fS = 48 kHz –0.2 dB |
Similar Part No. - TLV320AIC3104-Q1_16 |
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Similar Description - TLV320AIC3104-Q1_16 |
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