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TAS5720L Datasheet(PDF) 9 Page - Texas Instruments |
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TAS5720L Datasheet(HTML) 9 Page - Texas Instruments |
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9 / 52 page  9 TAS5720L, TAS5720M www.ti.com SLOS903B – MAY 2015 – REVISED FEBRUARY 2016 Product Folder Links: TAS5720L TAS5720M Submit Documentation Feedback Copyright © 2015–2016, Texas Instruments Incorporated 6.6 Timing Requirements MIN NOM MAX UNIT tACTIVE Shutdown to Active Time From deassertion of SDZ (both pin and I2C register bit) until the Class-D amplifier begins switching. 25 ms tWAKE Wake Time From the deassertion of SLEEP until the Class-D amplifier starts switching. 1 tSLEEP Sleep Time From the assertion of SLEEP until the Class-D amplifier stops switching. tvrmp + 1 tMUTE Play to Mute Time From the assertion of MUTE mode until the volume has ramped to the minimum. tvrmp tPLAY Un-Mute to Play Time From the deassertion of MUTE until the volume has returned to its current setting. tvrmp tSD Active to Shutdown Time From the assertion of SDZ (pin or I2C register bit) until the Class-D amplifier stops switching. tvrmp + 1 SERIAL AUDIO PORT tH_L Time high and low, BCLK, LRCLK, SDIN inputs 10 ns tSU tHLD Setup and hold time. LRCLK, SDIN input to BCLK edge. Input tRISE ≤ 1 ns, input tFALL ≤ 1 ns 5 ns Input tRISE ≤ 4 ns, input tFALL ≤ 4 ns 8 Input tRISE ≤ 8 ns, input tFALL ≤ 8 ns 12 tRISE Rise-time BCLK, LRCLK, SDIN inputs 8 ns tFALL Fall-time BCLK, LRCLK, SDIN inputs 8 I2C CONTROL PORT tBUS Bus free time between start and stop conditions 1.3 µs tHOLD1(I2C) Hold Time, SCL to SDA 80 ns tHOLD2(I2C) Hold Time, start condition to SCL 0.6 µs tSTART(I2C) I2C Startup Time after DVDD Power On Reset 12 ms tRISE(I2C) Rise Time, SCL and SDA 300 ns tFALL(I2C) Fall Time, SCL and SDA 300 ns tSU1(I2C) Setup, SDA to SCL 100 ns tSU2(I2C) Setup, SCL to start condition 0.6 µs tSU3(I2C) Setup, SCL to stop condition 0.6 µs tW(H) Required pulse duration, SCL "HIGH" 0.6 µs tW(L) Required pulse duration, SCL "LOW" 1.3 µs PROTECTION tFAULTZ Amplifier fault time-out period DC detect error 650 ms OTE or OCE fault 1.3 s |
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