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MB9AFA42MB Datasheet(PDF) 5 Page - SPANSION |
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5 / 125 page D a t a S h e e t 2 MB9AA40NB_DS706-00038-4v0-E, June 10, 2015 CONFIDENTIAL Features 32-bit ARM Cortex-M3 Core Processor version: r2p1 Up to 40 MHz Frequency Operation Integrated Nested Vectored Interrupt Controller (NVIC): 1 NMI (non-maskable interrupt) and 48 peripheral interrupts and 16 priority levels 24-bit System timer (Sys Tick): System timer for OS task management On-chip Memories [Flash memory] Dual operation Flash memory ・Dual Operation Flash memory has the upper bank and the lower bank. So, this series could implement erase, write and read operations for each bank simultaneously. Main area: Up to 256 Kbytes (Up to 240 Kbytes upper bank + 16 Kbytes lower bank) Work area: 32 Kbytes (lower bank) Read cycle: 0 wait-cycle Security function for code protection [SRAM] This Series on-chip SRAM is composed of two independent SRAM (SRAM0, SRAM1). SRAM0 is connected to I-code bus and D-code bus of Cortex-M3 core. SRAM1 is connected to System bus. SRAM0: Up to 16 Kbytes SRAM1: Up to 16 Kbytes External Bus Interface* Supports SRAM, NOR Flash memory device Up to 8 chip selects 8-/16-bit Data width Up to 25-bit Address bit Maximum area size : Up to 256 Mbytes Supports Address/Data multiplex Supports external RDY function * : MB9AFA41LB, FA42LB and FA44LB do not support External Bus Interface. LCD Controller (LCDC) Up to 40 SEG × 8 COM 8 COM or 4 COM mode can be selected. Built-in internal dividing resistor LCD drive power supply (bias) pin (VV4 to VV0) With blinking function |
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