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MB9AF1A2N Datasheet(PDF) 5 Page - SPANSION |
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5 / 101 page D a t a S h e e t 2 MB9A1A0N_DS706-00068-2v0-E, June 30, 2015 CONFIDENTIAL Features 32-bit ARM Cortex-M3 Core Processor version: r2p1 Up to 20 MHz Operation Frequency Integrated Nested Vectored Interrupt Controller (NVIC): 1 channel NMI (non-maskable interrupt) and 32 channels' peripheral interrupts and 8 priority levels 24-bit System timer (Sys Tick): System timer for OS task management On-chip Memories [Flash memory] Up to 128 Kbytes Read cycle: 0 wait-cycle Security function for code protection [SRAM] This series contains a total of up to 16 Kbyte on-chip SRAM that is connected to System bus of Cortex-M3 core. SRAM1: Up to 16 Kbytes Multi-function Serial Interface (Max 8 channels) Operation mode is selectable from the followings for each channel. UART CSIO I2C [UART] Full duplex double buffer Selection with or without parity supported Built-in dedicated baud rate generator External clock available as a serial clock Various error detection functions available (parity errors, framing errors, and overrun errors) [CSIO] Full duplex double buffer Built-in dedicated baud rate generator Overrun error detection function available [I 2C] Standard-mode (Max 100 kbps) / Fast-mode (Max 400 kbps) supported A/D Converter (Max 16 channels) [12-bit A/D Converter] Successive Approximation type Conversion time: Min 1.0 μs Priority conversion available (priority at 2levels) Scanning conversion mode Built-in FIFO for conversion data storage (for SCAN conversion: 16steps, for Priority conversion: 4steps) D/A Converter (Max 2 channels) R-2R type 10-bit resolution |
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