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PI6ULS5V9617AWE Datasheet(PDF) 7 Page - Pericom Semiconductor Corporation |
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PI6ULS5V9617AWE Datasheet(HTML) 7 Page - Pericom Semiconductor Corporation |
7 / 13 page ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| 2014-03-0003 PT0482-3 04/09/14 7 PI6ULS5V9617A Level Translating Fast-Mode Plus I 2C-bus/SMbus Repeater As with the standard I 2C-bus system, pull-up resistors are required to provide the logic HIGH levels on the buffered bus (standard open-collector configuration of the I 2C-bus). The size of these pull-up resistors depends on the system, but each side of the repeater must have a pull-up resistor. This part designed to work with Standard mode, Fast-mode and Fast-mode Plus I 2C-bus devices in addition to SMBus devices. Standard mode and Fast-mode I2C-bus devices only specify 3mA output drive; this limits the termination current to 3mA in a generic I 2C-bus system where Standard- mode devices, Fast-mode devices and multiple masters are possible. When only Fast-mode Plus devices are used with 30mA at 5 V drive strength, then lower value pull-up resistors can be used. The B-side RC should not be less than 67.5 ns because shorter RCs increase the turnaround bounce when the B-side transitions from being externally driven to pulled down by its offset buffer. Application Information A typical application is shown in Figure 9. In this example, the system master is running on a 3.3 V I 2C-bus while the slave is connected to a 1.2 V bus. Both buses run at 1MHz. Master devices can be placed on either bus. Figure 9: Typical Application The PI6ULS5V9617A is 5V tolerant, so it does not require any additional circuitry to translate between 0.6V to 5.5V bus voltages and 2.2 V to 5.5 V bus voltages. When port A of the PI6ULS5V9617A is pulled LOW by a driver on the I 2C-bus, a comparator detects the falling edge when it goes below 0.3VCC(A) and causes the internal driver on port B to turn on, causing port B to pull down to about 0.5 V. When port B of the PI6ULS5V9617A falls, first a CMOS hysteresis type input detects the falling edge and causes the internal driver on port A to turn on and pull the port A pin down to ground. In order to illustrate what would be seen in a typical application, refer to Figure 9 and Figure 10. If the bus master in Figure 9 were to write to the slave through the PI6ULS5V9617A, waveforms shown in Figure 9 would be observed on the A bus. This looks like a normal I 2C-bus transmission except that the HIGH level may be as low as 0.6V, and the turn on and turn off of the acknowledge signals are slightly delayed. On the B bus side of the PI6ULS5V9617A, the clock and data lines would have a positive offset from ground equal to the VOL of the PI6ULS5V9617A. After the eighth clock pulse, the data line will be pulled to the VOL of the slave device which is very close to ground in this example. At the end of the acknowledge, the level rises only to the LOW level set by the driver in the PI6ULS5V9617A for a short delay while the A bus side rises above 0.3VCC(A) then it continues HIGH. It is important to note that any arbitration or clock stretching events require that the LOW level on the B bus side at the input of the PI6ULS5V9617A (VIL) be at or below 0.4 V to be recognized by the PI6ULS5V9617A and then transmitted to the A bus side. Multiple PI6ULS5V9617A port A sides can be connected in a star configuration (Figure 10), allowing all nodes to communicate with each other. |
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