IS66WVD4M16ALL datasheet(11/52 Pages) ISSI

Part #	IS66WVD4M16ALL

Description	Single device supports asynchronous and burst operation

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Manufacturer	ISSI [Integrated Silicon Solution, Inc]

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IS66WVD4M16ALL

11

Rev.A | June 2011

www.issi.com - SRAM@issi.com

Asynchronous Mode

Asynchronous mode uses industry-standard SRAM control signals (CE#, ADV#, OE#,

WE#, UB#, and LB#). READ operations (Figure 4) are initiated by bringing CE#, ADV#,

UB# and LB# LOW while keeping OE# and WE# HIGH, and driving the address onto the

multiplexed address/data bus. ADV# is taken HIGH to capture the address, and OE# is

taken LOW. Valid data will be driven out of the I/Os after the specified access time has

elapsed.

WRITE operations (Figure 5) occur when CE#, ADV#, WE#, UB#, and LB# are driven LOW

with the address on the multiplexed address/data bus. ADV# is taken HIGH to capture

the address, then the write data is driven onto the bus. During asynchronous WRITE

operations, the OE# level is a “Don't Care,” and WE# will override OE#; however, OE#

must be HIGH while the address is driven onto the ADQ bus. The data to be written is

latched on the rising edge of CE#, WE#, UB#, and LB# (whichever occurs first).

During asynchronous operation, the CLK input must be held LOW. WAIT will be driven

during asynchronous READs, and its state should be ignored. WE# must not be held

LOW longer than tCEM.

Figure 4. Asynchronous Read Access Timing

Address

ADQ0-

ADQ15

ADV#

CE#

UB#/LB#

WAIT

OE#

WE#

HiZ

tVP

tAVS

tAVH

VALID

ADDRESS

VALID

ADDRESS

VALID

OUTPUT

tCO

tAADV

tOE

tHZ

tCVP

tOLZ

tBA

tAA

tBHZ

tOHZ

tOEW

tWZ

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IS66WVD4M16ALL Datasheet(PDF) 11 Page - Integrated Silicon Solution, Inc

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