9

IS66WV1M16EALL

IS66/67WV1M16EBLL

Rev. 0A | October 2014

www.issi.com - SRAM@issi.com

Symbol

Parameter

-55

-70

Unit

Notes

Min

Max

Min

Max

Write Cycle Time

55

-

70

-

ns

CS1#/CS2 to Write End

45

-

60

-

ns

Maximum CS1#/CS2 pulse width

-

15

-

15

us

Address Setup to Write Time

45

-

60

-

ns

Address Hold to End of Write

0

-

0

-

ns

Address Setup Time

0

-

0

-

ns

UB#/LB# Valid to End of Write

45

-

60

-

ns

WE# Pulse Width

45

-

60

-

ns

Data Setup Time

25

-

30

-

ns

UB#/LB# to High-Z output

0

-

0

-

ns

3

UB#/LB# to Low-Z output

-

20

-

30

ns

3

CS1# HIGH (CS2 LOW) time

5

-

5

-

ns

Notes:

1. Test conditions and output loading are specified in the AC Test Conditions and AC Test Loads (Figure 1) on page 5.

2. The internal write time is defined by the overlap of CS1#, UB#, LB# and WE# LOW, CS2 HIGH . All signals must be

in valid states to initiate a Write, but anyone can go inactive to terminate Write. The Data Input Setup and Hold timing are

referenced to the rising or falling edge of the signals that terminates the Write.

3. Tested with the load in Figure 2. Transition is measured ±100 mV from steady-state voltage. Not 100% tested.

5. Chip Select Active Time (both CS1# LOW and CS2 HIGH) must not be longer than tCMS of 15 us.