IS61QDPB44M18A/A1/A2

IS61QDPB42M36A/A1/A2

Integrated Silicon Solution, Inc.- www.issi.com

Rev. E

07/07/2014

11

Timing Reference Diagram for Truth Table

The Timing Reference Diagram for Truth Table is helpful in understanding the Clock and Write Truth Tables, as it

shows the cycle relationship between clocks, address, data in, data out, and control signals. Read command is issued

at the beginning of cycle “t”. Write command is issued at the beginning of cycle “t+1”.

DB

DB+1

DB+2

DB+3

QA

t + 1

t

t + 2

t + 3

t + 4

t + 5

A

B

Cycle

K Clock

K# Clock

R#

W#

Address

Data-In

Data-Out

QVLD

CQ Clock

CQ# Clock

2.5 Cycle Read Latency

QA+1

QA+2

QA+3

tCHQV

tQVLD

tQVLD