IS61QDPB44M18A/A1/A2

IS61QDPB42M36A/A1/A2

Integrated Silicon Solution, Inc.- www.issi.com

Rev. E

07/07/2014

8

Sequence3. /Doff is controlled but goes high before clock being stable.

Because DLL has a risk to be locked with the unstable clock, DLL needs to be reset and locked with the stable input.

a) K-stop to reset. If K or K# stays at VIH or VIL for more than 30nS, DLL will be reset and ready to re-lock. In tKC-

Lock period, DLL will be locked with a new stable value. Device can be ready for normal operation after that.

Note) All inputs including clocks must be either logically High or Low during Power On stage. Timing above shows only one of cases.

a) /Doff Low to reset. If /Doff toggled low to high, DLL will be reset and ready to re-lock. In tKC-Lock period, DLL will

be locked with a new stable value. Device can be ready for normal operation after that.

Note) Applying DLL reset sequences (sequence 3a, 3b) are also required when operating frequency is changed without power off.

Note) All inputs including clocks must be either logically High or Low during Power On stage. Timing above shows only one of cases.

Power On stage

Unstable Clock Period

K-Stop

Stable Clock period

Read to use

K

K#

Doff#

VDD

VDDQ

VREF

VIN

Power On stage

Unstable Clock Period

Doff reset DLL

Stable Clock period

Read to use

K

K#

Doff#

VDD

VDDQ

VREF

VIN

>30nS

>tKC-lock for device initialization

>tDoffLowToReset

>tKC-lock for device

initialization