IS61QDPB41M18A/A1/A2

IS61QDPB451236A/A1/A2

Integrated Silicon Solution, Inc.- www.issi.com

Rev. B

10/02/2014

1

1Mx18, 512Kx36

18Mb QUADP (Burst 4) SYNCHRONOUS SRAM

(2.5 Cycle Read Latency)

FEATURES



512Kx36 and 1Mx18 configuration available.



On-chip Delay-Locked Loop (DLL) for wide data

valid window.



Separate independent read and write ports with

concurrent read and write operations.



Synchronous pipeline read with late write operation.



Double Data Rate (DDR) interface for read and

write input ports.



2.5 cycle read latency.



Fixed 4-bit burst for read and write operations.



Clock stop support.



Two input clocks (K and K#) for address and control

registering at rising edges only.



Two echo clocks (CQ and CQ#) that are delivered

simultaneously with data.



Data Valid Pin (QVLD).



+1.8V core power supply and 1.5, 1.8V VDDQ, used

with 0.75, 0.9V VREF.



HSTL input and output interface.



Registered addresses, write and read controls, byte

writes, data in, and data outputs.



Full data coherency.



Boundary scan using limited set of JTAG 1149.1

functions.



Byte write capability.



Fine ball grid array (FBGA) package:

13mmx15mm and 15mmx17mm body size

165-ball (11 x 15) array



Programmable impedance output drivers via 5x

user-supplied precision resistor.



ODT (On Die Termination) feature is supported



The end of top mark (A/A1/A2) is to define options.

IS61QDPB451236A

:

Don’t care ODT function

and pin connection

IS61QDPB451236A 1 : Option1

IS61QDPB451236A 2 : Option2

Refer to more detail description at page 6 for each

ODT option.

DESCRIPTION

The 18Mb IS61QDPB451236A/A1/A2 and

IS61QDPB41M18A/A1/A2 are synchronous, high-

performance CMOS static random access memory (SRAM)

devices. These SRAMs have separate I/Os, eliminating the

need for high-speed bus turnaround. The rising edge of K

clock initiates the read/write operation, and all internal

operations are self-timed. Refer to the Timing Reference

Diagram for Truth Table for a description of the basic

operations of these QUADP (Burst of 4) SRAMs. Read and

write addresses are registered on alternating rising edges of

the K clock. Reads and writes are performed in double data

rate.

The following are registered internally on the rising edge of

the K clock:



Read/write address



Read enable



Write enable



Byte writes for burst addresses 1 and 3



Data-in for burst addresses 1 and 3

The following are registered on the rising edge of the K#

clock:



Byte writes for burst addresses 2 and 4



Data-in for burst addresses 2 and 4

Byte writes can change with the corresponding data-in to

enable or disable writes on a per-byte basis. An internal write

buffer enables the data-ins to be registered one cycle after

the write address. The first data-in burst is clocked one cycle

later than the write command signal, and the second burst is

timed to the following rising edge of the K# clock. Two full

clock cycles are required to complete a write operation.

During the burst read operation, the data-outs from the first

and third bursts are updated from output registers of the third

and fourth rising edges of the K# clock (starting 2.5 cycles

later after read command). The data-outs from the second

and fourth bursts are updated with the fourth and fifth rising

edges of the K clock where the read command receives at

the first rising edge of K. Two full clock cycles are required to

complete a read operation.

The device is operated with a single +1.8V power supply

and is compatible with HSTL I/O interfaces.

NOVEMBER 2014

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