IS61QDP2B42M18A/A1/A2

IS61QDP2B41M36A/A1/A2

Integrated Silicon Solution, Inc.- www.issi.com

Rev. B

12/15/2014

7

Power-Up and Power-Down Sequences

REF

IN

Notes:

After power and clock signals are stabilized, device can be ready for normal operation after tKC-Lock cycles. In tKC-

lock cycle period, device initializes internal logics and locks DLL. Depending on /Doff status, locking DLL will be

skipped. The following timing pictures are possible examples of power up sequence.

Sequence1. /Doff is fixed low

After tKC-lock cycle of stable clock, device is ready for normal operation.

Power On stage

Unstable Clock Period

Stable Clock period

Read to use

K

K#

VDD

VDDQ

VREF

VIN

Note) All inputs including clocks must be either logically High or Low during Power On stage. Timing above shows only one of cases.

Sequence2. /Doff is controlled and goes high after clock being stable.

Power On stage

Unstable Clock Period

Stable Clock period

Read to use

K

K#

Doff#

VDD

VDDQ

VREF

VIN

Note) All inputs including clocks must be either logically High or Low during Power On stage. Timing above shows only one of cases.

>tKC-lock for device initialization

>tKC-lock for device initialization