IS61QDP2B42M18A/A1/A2

IS61QDP2B41M36A/A1/A2

Integrated Silicon Solution, Inc.- www.issi.com

Rev. B

12/15/2014

4

SRAM Features description

Block Diagram

Data

Register

Address

Register

Control

Logic

D (Data-In)

36 (18)

18 (19)

Address

4 (2)

R#

W#

Clock

Generator

Doff#

K

K#

1M x 36

(2M x 18)

Memory Array

Write

Driver

Select Output Control

Output

Register

18 (19)

72 (36)

72 (36)

72 (36)

72 (36)

72 (36)

144 (72)

36 (18)

Q (Data-out)

QVLD

CQ, CQ#

(Echo Clocks)

2

36 (18)

QVLD

CQ, CQ#

(Echo Clocks)

2

Note: Numerical values in parentheses refer to the x18 device configuration.

Read Operations

The SRAM operates continuously in a burst-of-four mode. Read cycles are started by registering R# in active low state

at the rising edge of the K clock. R# can be activated every other cycle because two full cycles are required to

complete the burst of four in DDR mode. A set of free-running echo clocks, CQ and CQ#, are produced internally with

timings identical to the data-outs. The echo clocks can be used as data capture clocks by the receiver device.

The data corresponding to the first address is clocked two cycles later by the rising edge of the K clock. The data

corresponding to the second burst is clocked two and half cycles later by the following rising edge of the K# clock. The

third data-out is clocked by the subsequent rising edge of the K clock, and the fourth data-out is clocked by the

subsequent rising edge of the K# clock.

A NOP operation (R# is high) does not terminate the previous read.

Write Operations

Write operations can also be initiated at every other rising edge of the K clock whenever W# is low. The write address

is provided simultaneously. Again, the write always occurs in bursts of four.

The write data is provided in a ‘late write’ mode; that is, the data-in corresponding to the first address of the burst, is

presented one cycle later or at the rising edge of the following K clock. The data-in corresponding to the second write

burst address follows next, registered by the rising edge of K#. The third data-in is clocked by the subsequent rising

edge of the K clock, and the fourth data-in is clocked by the subsequent rising edge of the K# clock.