IS61QDP2B22M18A/A1/A2

IS61QDP2B21M36A/A1 /A2

Integrated Silicon Solution, Inc.- www.issi.com

Rev. B

10/02/2014

10

State Diagram

Power-Up

Read NOP

Write NOP

Load New Read

Address

Load New Write

Address

DDR Read

DDR Write

Read#

Write#

Read

Write

Read

Write

Always

(fixed)

Always

(fixed)

Write#

Read#

Notes:

1.

Internal burst counter is fixed as two-bit linear; that is when first address is A0+0, next internal burst addresses are A0+1.

2.

Read refers to read active status with R# = LOW. Read# refers to read inactive status with R# = HIGH.

3.

Write refers to write active status with W# = LOW. Write# refers to write inactive status with W# = HIGH.

4.

The read and write state machines can be active simultaneously.

5.

State machine control timing sequence is controlled by K.