IS61QDB21M18A

IS61QDB251236A

Integrated Silicon Solution, Inc.- www.issi.com

Rev. B

10/02/2014

11

Timing Reference Diagram for Truth Table

The Timing Reference Diagram for Truth Table is helpful in understanding the Clock and Write Truth Tables, as it

shows the cycle relationship between clocks, address, data in, data out, and control signals. Read command is issued

at the beginning of cycle “t”. Write command is issued at the beginning of cycle “t+1”.

DB

DB+1

DD

DD+1

QA

QA+1

QC

QC+1

t + 1

t

t + 2

t + 3

t + 4

t + 5

A

C

Cycle

K Clock

K# Clock

R#

W#

Address

Data-In

Data-Out

C Clock

C# Clock

CQ Clock

CQ# Clock

B

D

Clock Truth Table

(Use the following table with the

.)

Mode

Clock

Controls

Data In

Data Out

K

R#

W#

Stop Clock

Stop

X

X

Previous State

Previous State

Previous State

Previous State

No Operation (NOP)

L → H

H

H

X

X

High-Z

High-Z

Read A

L → H

L

X

X

X

Write B

L → H

X

L

X

X

Notes:

1.

Internal burst counter is always fixed as two-bit.

2.

X = “don’t care”; H = logic “1”; L = logic “0”.

3.

A read operation is started when control signal R# is active low

4.

A write operation is started when control signal W# is active low.