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ADC12062BIVF Datasheet(PDF) 4 Page - National Semiconductor (TI)

[Old version datasheet] Texas Instruments acquired National semiconductor.
Part # ADC12062BIVF
Description  12-Bit, 1 MHz, 75 mW A/D Converter
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Manufacturer  NSC [National Semiconductor (TI)]
Direct Link  http://www.national.com
Logo NSC - National Semiconductor (TI)

ADC12062BIVF Datasheet(HTML) 4 Page - National Semiconductor (TI)

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AC Electrical Characteristics The following specifications apply for DVCC e AVCC ea5V
VREFa(SENSE) ea4096V VREFb(SENSE) e AGND and fs e 1 MHz unless otherwise specified Boldface limits apply
for TA e TJ from TMIN to TMAX all other limits TA e TJ ea25 C
Symbol
Parameter
Conditions
Typ
Limit
Units
(Note 7)
(Note 8)
(Limits)
fs
Maximum Sampling Rate
1
MHz (min)
(1tTHROUGHPUT)
tCONV
Conversion Time
740
600
ns (min)
(SH Low to EOC High)
980
ns (max)
tAD
Aperture Delay
20
ns
(SH Low to Input Voltage Held)
tSH
SH Pulse Width
5
ns (min)
550
ns (max)
tEOC
SH Low to EOC Low
95
60
ns (min)
125
ns (max)
tACC
Access Time
CL e 100 pF
10
20
ns (max)
(RD Low or OE High to Data Valid)
t1H t0H
TRI-STATE Control
RL e 1k CL e 10 pF
25
40
ns (max)
(RD High or OE Low to Databus TRI-STATE)
tINTH
Delay from RD Low to INT High
CL e 100 pF
35
60
ns (max)
tINTL
Delay from EOC High to INT Low
CL e 100 pF
b
25
b
35
ns (min)
b
10
ns (max)
tUPDATE
EOC High to New Data Valid
5
15
ns (max)
tMS
Multiplexer Address Setup Time
50
ns (min)
(MUX Address Valid to EOC Low)
tMH
Multiplexer Address Hold Time
50
ns (min)
(EOC Low to MUX Address Invalid)
tCSS
CS Setup Time
20
ns (min)
(CS Low to RD Low SH Low or OE High)
tCSH
CS Hold Time
20
ns (min)
(CS High after RD High SH High or OE Low)
tWU
Wake-Up Time
1
m
s
(PD High to First SH Low)
Note 1
Absolute Maximum Ratings indicate limits beyond which damage to the device may occur Operating Ratings indicate conditions for which the device is
functional These ratings do not guarantee specific performance limits however For guaranteed specifications and test conditions see the Electrical Characteris-
tics The guaranteed specifications apply only for the test conditions listed Some performance characteristics may degrade when the device is not operated under
the listed test conditions
Note 2
All voltages are measured with respect to GND (GND e AGND e DGND) unless otherwise specified
Note 3
When the input voltage (VIN) at any pin exceeds the power supply rails (VIN k GND or VIN l VCC) the absolute value of current at that pin should be
limited to 25 mA or less The 50 mA package input current limits the number of pins that can safely exceed the power supplies with an input current of 25 mA to
two
Note 4
The maximum power dissipation must be derated at elevated temperatures and is dictated by TJMAX iJA and the ambient temperature TA The maximum
allowable power dissipation at any temperature is PD e (TJMAX b TA) iJA or the number given in the Absolute Maximum Ratings whichever is lower iJA for the V
(PLCC) package is 55 CW iJA for the VF (PQFP) package is 62 CW In most cases the maximum derated power dissipation will be reached only during fault
conditions
4


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