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IS61DDP2B24M18A Datasheet(PDF) 6 Page - Integrated Silicon Solution, Inc |
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IS61DDP2B24M18A Datasheet(HTML) 6 Page - Integrated Silicon Solution, Inc |
6 / 31 page IS61DDP2B24M18A/A1/A2 IS61DDP2B22M36A/A1/A2 Integrated Silicon Solution, Inc.- www.issi.com Rev. A 09/20/2014 6 ODT (On Die Termination) On Die Termination (ODT) is a feature that allows a SRAM to turn on/off termination resistance for ODT pins. The ODT feature is designed to improve signal integrity of the memory channel by allowing the SRAM controller to turn on/off termination resistance independently for any or all SRAM devices. ODT can have three status, High, Low, and Floating. Each status can have different ODT termination values which tracks the value of RQ (See the picture below) In DDR-IIP devices having common I/O bus, ODT is automatically enabled at the write operation of SRAM and disabled at the read operation of SRAM. Fig1. Functional representation of ODT Notes 1. Allowable range of RQ to guarantee impedance matching a tolerance of ±20% is 175 Ω<RQ<350Ω. 2. Allowable range of RQ to guarantee impedance matching a tolerance of ±20% is 175 Ω<RQ<250Ω. 3. ODT control pin is connected to VDDQ through 3.5k Ω. Therefore it is recommended to connect it to VSS through less than 100 Ω to make it low. 4. ODT control pin is connected to VSS through 3.5k Ω. Therefore it is recommended to connect it to VDDQ through less than 100 Ω to make it high. R1 R2 R3 Option1 3 0.3x RQ 1 0.6x RQ 2 0.6x RQ 2 Option2 4 ODT disable 0.6x RQ 2 ODT disable PAD ODT=L ODT=L ODT=H ODT=H ODT=Floating ODT=Floating VDDQ VSS VDDQ VSS VDDQ VSS R1x2 R1x2 R2x2 R2x2 R3x2 R3x2 |
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