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IS61DDB24M18A Datasheet(PDF) 8 Page - Integrated Silicon Solution, Inc |
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IS61DDB24M18A Datasheet(HTML) 8 Page - Integrated Silicon Solution, Inc |
8 / 29 page IS61DDB24M18A IS61DDB22M36A Integrated Silicon Solution, Inc.- www.issi.com Rev. A 08/15/2014 8 Application Example The following figure depicts an implementation of four 2M x 18 DDR-II SRAMs with common I/Os. In this application example, the second pair of C and C# clocks is delayed such that the return data meets the data setup and hold times at the bus master. SRAM #1 SA R/W# LD# BWx# K/K# C/C# DQ CQ/CQ# ZQ RQ = 250 Ω SRAM #4 ZQ RQ = 250 Ω Data-In&Data Out Address SRAM #1 CQ Input SRAM #4 CQ Input Read&Write Control New Address Control Byte Write Control Source CLK Return CLK Memory Controller Vt Vt R R = 50 Ω R Vt = V REF SA R/W# LD# BWx# K/K# C/C# DQ CQ/CQ# Vt R |
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