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IS61DDB24M18A Datasheet(PDF) 10 Page - Integrated Silicon Solution, Inc |
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IS61DDB24M18A Datasheet(HTML) 10 Page - Integrated Silicon Solution, Inc |
10 / 29 page IS61DDB24M18A IS61DDB22M36A Integrated Silicon Solution, Inc.- www.issi.com Rev. A 08/15/2014 10 Timing Reference Diagram for Truth Table The Timing Reference Diagram for Truth Table is helpful in understanding the Clock and Write Truth Tables, as it shows the cycle relationship between clocks, address, data in, data out, and control signals. Read command is issued at the beginning of cycle “t”. Write command is issued at the beginning of cycle “t+1”. DB DB+1 QA QA+1 t + 1 t t + 2 t + 3 t + 4 t + 5 A B Cycle K Clock K# Clock LD# R/W# BWx# Address Data- In/Out(DQ) CQ CQ# C Clock C# Clock tCHQV Clock Truth Table (Use the following table with the Timing Reference Diagram for Truth Table.) Mode Clock Controls Data Out / Data In K LD# R/W# QA / DB QA+1 / DB+1 Stop Clock Stop X X Previous State Previous State No Operation (NOP) L → H H X High-Z High-Z Read A L → H L H DOUT at C# (t+1.5) ↑ DOUT at C (t+2.0) ↑ Write B L → H L L DB at K (t+4.0) ↑ DB at K# (t+4.5) ↑ Notes: 1. X = “don’t care”; H = logic “1”; L = logic “0”. 2. A read operation is started when control signal R/W# is active high. 3. A write operation is started when control signal R/W# is active low. 4. Before entering into stop clock, all pending read and write commands must be completed. 5. For timing definitions, refer to the AC Timing Characteristics table. Signals must meet AC specifications at timings indicated in parenthesis with respect to switching clocks K,K#,C, and C#. |
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