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PI3EQXDP1201 Datasheet(PDF) 6 Page - Pericom Semiconductor Corporation |
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PI3EQXDP1201 Datasheet(HTML) 6 Page - Pericom Semiconductor Corporation |
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6 / 16 page  PI3EQXDP1201 3.3V, 4-Ch DisplayPort 1.2 Redriver with AUX Listener/AutoTest mode 6 www.pericom.com 02/27/15 COMPANY CONFIDENTIAL Functional Description Intelligent Power Management Pericom’sblockbaseddesignandintelligentdetectionscheme allow portions, or all of the IC, to be disabled for power sav- ings. For example, in DP mode, if only one or two lanes are active,theotherlaneswillbeautomaticallypoweredoff.Ifthere is no input video signal the entire IC will be powered down. If there is no monitor detected, Pericom’s PI3EQXDP1201 can also automatically power down the IC. This intelligent power management concept not only saves system power, but also stops the device from outputting useless data or noise when no signal is present at the input of the IC. The power-down mode can also be entered using hard pin EN- ABLE, or through DPCD register (AUX link training) DisplayPort AUX Listener PI3EQXDP1201 integrates an AUX listener(decoder), which enables the device to receive and deci- pher all AUX link training data and use this ex- tracted information for its own configuration. The intercepted DPCD data is used to adjust the active lane count, output swing level, output pre-emphasis level, and to manage the device’s D3 power saving state. AUX Listener Specification DP AUX listener will support Native AUX CH Syntax. Mapping of I2C onto AUX CH Syntax is not supported. AUX listener monitors AUX channel from requester and replier for transactions and stored AUX command from requester and reply command from sinks that are related to the link settings. AUX listener recovered the clock from AUX data input by cycle counting the synchronization pulse at the beginning of the AUX cycle. In a AUX write request cycle, the AUX address compare the addresses with the following registers’ address, data is extracted and stored into the respective registers when the addresses matches. These registers are set during link training se- quence following hot plug detection. 00100h Data Rate Register 00101h LANE_COUNT_SET 00103h TRAINING_LANE0_SET 00104h TRAINING_LANE1_SET 00105h TRAINING_LANE2_SET 00106h TRAINING_LANE3_SET 00260h Sink Test request response 00600h Power Down The AUX listener support Sink request Test sequence. After HPD IRQ event and DP source read 00201h AUX register and if bit 1 is high, the DP source will enter a Sink request test mode and initiate a sequence of AUX read request cycle. During the read cycle, data matching the fol- lowing registers address are stored in the listener. 00206h ADJUST_REQUEST_LANE0_1 00207h ADJUST_REQUEST_LANE2_3 00218h Test Request 00219h Test link rate 00220h Test Lane count After the read request cycle, the DP source will write 1 to Bit 0 register 00260h if the DP source enters sink request mode, or 1 to Bit 1 of register 00260h if the source declined the sink test request. The data stored in registers 002xx above will override the value set in 00101h to 00106h reg- isters when the sink entered the Sink Test mode. Sink Test Request Acknowledgement 00260h mode Buffer configuration outputs xxxxxx00b No action 00100 : 00106h xxxxxx01b Sink Test mode 00206h,00207h,00219h,00220h Override 00100,1,3,4,5,6h register settings xxxxxx10b Sink test mode declined 00100h : 00106h xxxxxx11b Not Legal code 00100h : 00106h 15-0021 |
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