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ADC1175CIJMX Datasheet(PDF) 3 Page - National Semiconductor (TI) |
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ADC1175CIJMX Datasheet(HTML) 3 Page - National Semiconductor (TI) |
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3 / 19 page  Pin Descriptions and Equivalent Circuits (Continued) Pin No. Symbol Equivalent Circuit Description 17 V RT Analog Input that is the high (top) side of the reference ladder of the ADC. Nominal range is 1.0V to AV DD. Voltage on VRT and VRB inputs define the V IN conversion range. Bypass well. See Section 2.0 for more information. 23 V RB Analog Input that is the low (bottom) side of the reference ladder of the ADC. Nominal range is 0V to 4.0V. Voltage on V RT and VRB inputs define the VIN conversion range. Bypass well. See Section 2.0 for more information. 22 V RBS Reference Bottom Bias with internal pull down resistor. Short to V RB to self bias the reference ladder. 1OE CMOS/TTL compatible Digital input that, when low, enables the digital outputs of the ADC1175. When high, the outputs are in a high impedance state. 12 CLK CMOS/TTL compatible digital clock Input. V IN is sampled on the falling edge of CLK input. 3 thru 10 D0-D7 Conversion data digital Output pins. D0 is the LSB, D7 is the MSB. Valid data is output just after the rising edge of the CLK input. These pins are enabled by bringing the OE pin low. 11, 13 DV DD Positive digital supply pin. Connect to a clean, quiet voltage source of +5V. AV DD and DVDD should have a common source and be separately bypassed with a 10µF capacitor and a 0.1µF ceramic chip capacitor. See Section 3.0 for more information. www.national.com 3 |
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