IS42VS16400E-75BL datasheet(8/58 Pages) ISSI

Part #	IS42VS16400E-75BL

Description	Random column address every clock cycle

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Manufacturer	ISSI [Integrated Silicon Solution, Inc]

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IS42VS16400E

8

Integrated Silicon Solution, Inc. — www.issi.com

Rev. A

05/15/09

TRUTH TABLE – CKE (1-4)

CURRENT STATE

COMMANDn

ACTIONn

CKEn-1

CKEn

Power-Down

X

MaintainPower-Down

L

SelfRefresh

X

MaintainSelfRefresh

L

ClockSuspend

X

MaintainClockSuspend

L

DeepPower-Down(8)

X

MaintainDeepPower-Down

L

Power-Down(5)

COMMANDINHIBITorNOP

ExitPower-Down

L

H

DeepPower-Down(8)

X

ExitDeepPower-Down

L

H

SelfRefresh(6)

COMMANDINHIBITorNOP

ExitSelfRefresh

L

H

Clock Suspend(7)

X

ExitClockSuspend

L

H

AllBanksIdle

COMMANDINHIBITorNOP

Power-DownEntry

H

L

AllBanksIdle(8)

BURSTTERMINATE

DeepPower-DownEntry

H

L

AllBanksIdle

AUTOREFRESH

SelfRefreshEntry

H

L

ReadingorWriting

VALID

ClockSuspendEntry

H

L

See TRUTH TABLE – CURRENT STATE BANK n, COMMAND TO BANK

H

NOTES:

1. CKEnisthelogicstateofCKEatclockedgen;CKEn-1 wasthestateofCKEatthepreviousclockedge.

2. CurrentstateisthestateoftheSDRAMimmediatelypriortoclockedgen.

3. COMMANDnisthecommandregisteredatclockedgen,andACTONnisaresultofCOMMANDn.

4. Allstatesandsequencesnotshownareillegalorreserved.

5. Exitingpower-downatclockedgen will put the device in the all banks idle state in time for clock edge n+1 (provided that tcks is

met).

6. Exitingselfrefreshatclockedgen will put the device in all banks idle state once txsrismet.COMMANDINHIBITorNOP

commands should be issued on clock edges occurring during the txsrperiod.AminimumoftwoNOPcommandsmustbesent

during txsr period.

7. Afterexitingclocksuspendatclockedgen,thedevicewillresumeoperationandrecognizethenextcommandatclockedge

n+1.

8.DeepPower-DownisapowersavingfeatureofthismobileSDRAMdevice.ThiscommandisBURSTTERMINATEwhenCKEis

HIGHandDEEPPOWER-DOWNwhenCKEisLOW.

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IS42VS16400E-75BL Datasheet(PDF) 8 Page - Integrated Silicon Solution, Inc

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