FEATURES

• Single Power Supply Operation

- Low voltage range: 2.70 V - 3.60 V

• Memory Organization

- IS39LV512: 64K x 8 (512 Kbit)

- IS39LV010: 128K x 8 (1 Mbit)

- IS39LV040: 512K x 8 (4 Mbit)

• High Performance Read

- 70 ns access time

• Cost Effective Sector/Block Architecture

- Uniform 4 Kbyte sectors

- Uniform 64 Kbyte blocks (sector group - except

IS39LV512)

• Data# Polling and Toggle Bit Features

• Hardware Data Protection

• Automatic Erase and Byte Program

- Build-in automatic program verification

- Typical 16 µs/byte programming time

- Typical 55 ms sector/block/chip erase time

• Low Power Consumption

- Typical 4 mA active read current

- Typical 8 mA program/erase current

- Typical 0.1 µA CMOS standby current

• High Product Endurance

- Guarantee 100,000 program/erase cycles per

single sector (preliminary)

- Minimum 20 years data retention

• Industrial Standard Pin-out and Packaging

- 32-pin (8 mm x 14 mm) VSOP

- 32-pin PLCC

- Optional lead-free (Pb-free) package

• Operation temperature range

- IS39LV512/010

- IS39LV040

GENERAL DESCRIPTION

The IS39LV512/010/040 are 512 Kbit/1 Mbit/4 Mbit 3.0 Volt-only Flash Memories. These devices are designed

to use a single low voltage, range from 2.70 Volt to 3.60 Volt, power supply to perform read, erase and program

be programmed in standard EPROM programmers as well.

The memory array of IS39LV512 is divided into uniform 4 Kbyte sectors for data or code storage. The memory

arrays of IS39LV010/040 are divided into uniform 4 Kbyte sectors or uniform 64 Kbyte blocks (sector group -

consists of sixteen adjacent sectors). The sector or block erase feature allows users to flexibly erase a memory

area as small as 4 Kbyte or as large as 64 Kbyte by one single erase operation without affecting the data in

others. The chip erase feature allows the whole memory array to be erased in one single erase operation. The

devices can be programmed on a byte-by-byte basis after performing the erase operation.

The devices have a standard microprocessor interface as well as a JEDEC standard pin-out/command set. The

program operation is executed by issuing the program command code into command register. The internal control

logic automatically handles the programming voltage ramp-up and timing. The erase operation is executed by

issuing the chip erase, block, or sector erase command code into command register. The internal control logic

automatically handles the erase voltage ramp-up and timing. The preprogramming on the array which has not

been programmed is not required before an erase operation. The devices offer Data# Polling and Toggle Bit

functions, the progress or completion of program and erase operations can be detected by reading the Data#

Polling on I/O7 or the Toggle Bit on I/O6.

The IS39LV512/010/040 are manufactured on pFLASH™’s advanced nonvolatile CMOS technology. The devices

are offered in 32-pin VSOP and PLCC packages with 70 ns access time.

512 Kbit / 1Mbit / 4Mbit 3.0 Volt-only CMOS Flash Memory

IS39LV512 / IS39LV010 / IS39LV040

Integrated Silicon Solution, Inc. — www.issi.com

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Rev.  A

04/24/2013