Typical Performance Characteristics

Functional Description

The ADC1061 digitizes an analog input signal to 10 bits ac-

curacy by performing two lower-resolution “flash” conver-

sions. The first flash conversion provides the six most signifi-

cant bits (MSBs) of data, and the second flash conversion

provides the four least significant bits (LSBs).

Figure 3 is a simplified block diagram of the converter. Near

the center of the diagram is a string of resistors. At the bot-

tom of the string of resistors are 16 resistors, each of which

has a value 1/1024th the resistance of the whole resistor

string. These lower 16 resistors (the LSB Ladder) therefore

have a voltage drop of 16/1024, or 1/64th of the total refer-

ence voltage (V

of the resistor string is made up of eight groups of eight resis-

tors connected in series. These comprise the MSB Ladder.

Each section of the MSB Ladder has 1/8th of the total refer-

ence voltage across it, and each of the MSB resistors has

1/64th of the total reference voltage across it. Tap points

across all of these resistors can be connected, in groups, to

the sixteen comparators at the right of the diagram.

On the left side of the diagram is a string of seven resistors

connected between V

pare the input voltage with the tap voltages on the resistor

string to provide an estimate of the input voltage. This esti-

mate is then used to control the multiplexer that connects the

MSB Ladder to the sixteen comparators on the right. Note

that the comparators on the left needn’t be very accurate;

they simply provide an estimate of the input voltage. Only the

sixteen comparators on the right and the six on the left are

necessary to perform the initial six-bit flash conversion, in-

stead of the 64 comparators that would be required using

conventional half-flash methods.

To perform a conversion, the estimator compares the input

voltage with the tap voltages on the seven resistors on the

left. The estimator decoder then determines which MSB Lad-

der tap points will be connected to the sixteen comparators

on the right. For example, assume that the estimator deter-

mines that V

timator decoder will instruct the comparator mux to connect

the 16 comparators to the taps on the MSB Ladder between

10/16 and 14/16 of VREF. The 16 comparators will then per-

form the first flash conversion. Note that since the compara-

tors are connected to Ladder voltages that extend beyond

the range indicated by the estimator circuit, errors in the es-

timator as large as 1/16 of the reference voltage (64 LSBs)

will be corrected. This first flash conversion produces the six

most significant bits of data.

Zero (Offset) Error

vs Reference Voltage

DS010559-9

Linearity Error vs

Reference Voltage

DS010559-10

Mode 1 Conversion Time

vs Temperature

DS010559-11

Mode 2 Conversion Time

vs Temperature

DS010559-12

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