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TMS320C5533AZHHA05 Datasheet(PDF) 2 Page - Texas Instruments |
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TMS320C5533AZHHA05 Datasheet(HTML) 2 Page - Texas Instruments |
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2 / 156 page  TMS320C5535, TMS320C5534, TMS320C5533, TMS320C5532 SPRS737C – AUGUST 2011 – REVISED APRIL 2014 www.ti.com 1.2 Applications • Wireless Audio Devices (for example, Headsets, • Voice Applications Microphones, Speakerphones) • Industrial Controls • Echo Cancellation Headphones • Fingerprint Biometrics • Portable Medical Devices • Software-defined Radio 1.3 Description These devices are members of TI's C5000™ fixed-point Digital Signal Processor (DSP) product family and are designed for low-power applications. The fixed-point DSP is based on the TMS320C55x DSP generation CPU processor core. The C55x DSP architecture achieves high performance and low power through increased parallelism and total focus on power savings. The CPU supports an internal bus structure that is composed of one program bus, one 32- bit data read bus and two 16-bit data read buses, two 16-bit data write buses, and additional buses dedicated to peripheral and DMA activity. These buses provide the ability to perform up to four 16-bit data reads and two 16-bit data writes in a single cycle. The device also includes four DMA controllers, each with 4 channels, providing data movement for 16-independent channel contexts without CPU intervention. Each DMA controller can perform one 32-bit data transfer per cycle, in parallel and independent of the CPU activity. The C55x CPU provides two multiply-accumulate (MAC) units, each capable of 17-bit x 17-bit multiplication and a 32-bit add in a single cycle. A central 40-bit arithmetic and logic unit (ALU) is supported by an additional 16-bit ALU. Use of the ALUs is under instruction set control, providing the ability to optimize parallel activity and power consumption. These resources are managed in the Address Unit (AU) and Data Unit (DU) of the C55x CPU. The C55x CPU supports a variable byte width instruction set for improved code density. The Instruction Unit (IU) performs 32-bit program fetches from internal or external memory and queues instructions for the Program Unit (PU). The PU decodes the instructions, directs tasks to the AU and DU resources, and manages the fully protected pipeline. Predictive branching capability avoids pipeline flushes on execution of conditional instructions. The general-purpose input and output functions, along with the 10-bit SAR ADC on the TMS320C5535, provide sufficient pins for status, interrupts, and bit I/O for LCD displays, keyboards, and media interfaces. Serial media is supported through two secure digital (SD) peripherals, four Inter-IC Sound (I2S Bus) modules, one serial port interface (SPI) with up to four chip selects, one I2C multimaster and slave interface, and a universal asynchronous receiver/transmitter (UART) interface. Additional peripherals include: a high-speed Universal Serial Bus (USB 2.0) device mode only (not available on TMS320C5532), a real-time clock (RTC), three general-purpose timers with one configurable as a watchdog timer, and an analog phase-locked loop (APLL) clock generator. In addition, the TMS320C5535 includes a tightly coupled FFT Hardware Accelerator. The tightly coupled FFT Hardware Accelerator supports 8- to 1024-point (in power of 2) real and complex-valued FFTs. Furthermore, the device includes the following three integrated LDOs to power different sections of the device. ANA_LDO (all devices) provides 1.3 V to the DSP PLL (VDDA_PLL), SAR, and power-management circuits (VDDA_ANA). 2 Device Overview Copyright © 2011–2014, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TMS320C5535 TMS320C5534 TMS320C5533 TMS320C5532 |
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