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TMS320C6655CZH25 Datasheet(PDF) 5 Page - Texas Instruments |
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TMS320C6655CZH25 Datasheet(HTML) 5 Page - Texas Instruments |
5 / 245 page TMS320C6655, TMS320C6657 www.ti.com SPRS814B – MARCH 2012 – REVISED APRIL 2015 2 Revision History NOTE: Page numbers for previous revisions may differ from page numbers in the current version. Changes from September 1, 2012 to April 24, 2015 Page • Removed Security/Key Manager from Figure 1-1 ................................................................................ 3 • Removed "Secure ROM Boot" and changed "Public ROM Boot" to "ROM Boot" in Section 3.5 ......................... 15 • Added Boot Parameter Table section ............................................................................................ 28 • Updated OUTPUT_DIVIDE default value and PLL clock formula in PLL Settings section ................................ 37 • Clarified SmartReflex pin output type ............................................................................................. 53 • Removed SECURITY information from Figure 3-31 ............................................................................ 66 • Corrected EMAC User's Guide link in Related Documentation section ...................................................... 67 • Added DDR3PLLCTL1 register to Device Status Control Registers table ................................................... 71 • Updated PKTDMA_PRI_ALLOC register to be CHIP_MSIC_CTL register with new bit field added. .................... 72 • Corrected SmartReflex peripheral I/O Buffer Type from LVCMOS category to Open drain ............................. 115 • Updated Power Domain 12 to be VCP2_B from VCP2. Changed all references to VCP20, and VCP2-A to VCP2_A. Changed all references to VCP21, and VCP2-B to VCP2_B. ................................................... 124 • Updated ”slow peripherals” in SYSCLK7 description ........................................................................ 136 • Updated BWADJ value setting description in Main/DDR3 PLL contol registers ........................................... 148 • Updated all SerDes clocks to discrete frequencies in the Clock Input Timing Requirements table .................... 149 • Corrected differential clock rise and fall time in the PLL timing table for the clock inputs that feed into the LJCB clock buffers ........................................................................................................................ 149 • Added note to DDR3 PLL initialization sequence ............................................................................. 152 • Clarified table caption and first column heading ............................................................................... 160 • Updated event ”po_vp_smpsack_intr” to be Reserved in CIC2 event table ............................................... 174 • Corrected MPU0 Memory Protection End Address from 0x026203FF to 0x026207FF .................................. 183 • Removed SECURITY LEVEL column from Table 8-45 ...................................................................... 184 • Updated/Changed Bit 7 of Table 8-55 from "NS" to "Reserved" ............................................................ 195 • Added MPU Registers Reset Values section .................................................................................. 196 • Updated the Min/Max values of EMIF read cycle time and write cycle time ............................................... 213 • Updated Timer number description across the data manual ................................................................. 224 • Changed all footnote references from CORECLK to SYSCLK1 ............................................................. 225 • Updated the descriptions of how Semaphore module is accessible ........................................................ 226 • Corrected McBSP FIFO Control and Status Register address to be 0x021B6000 for McBSP0 and 0x021BA000 for McBSP1 ......................................................................................................................... 227 • Corrected McBSP FIFO Data Register address to be 0x22400000 for McBSP1 ......................................... 227 • Updated Trace Electrical Timing tables and Timing diagrams ............................................................... 237 Copyright © 2012–2015, Texas Instruments Incorporated Revision History 5 Submit Documentation Feedback |
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