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TMS320C5545AZQW10 Datasheet(PDF) 2 Page - Texas Instruments |
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TMS320C5545AZQW10 Datasheet(HTML) 2 Page - Texas Instruments |
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2 / 128 page  2 TMS320C5545 SPRS853C – JULY 2013 – REVISED MARCH 2016 www.ti.com Submit Documentation Feedback Product Folder Links: TMS320C5545 Device Overview Copyright © 2013–2016, Texas Instruments Incorporated 1.2 Applications • Wireless Audio Devices (for Example, Headsets, Microphones, Speakerphones) • Echo Cancellation Headphones • Portable Medical Devices • Voice Applications • Industrial Controls • Fingerprint Biometrics • Software-Defined Radio 1.3 Description These devices are members of TI's C5000™ fixed-point digital signal processor (DSP) product family and are designed for low-power applications. The fixed-point DSP is based on the TMS320C55x DSP generation CPU processor core. The C55x DSP architecture achieves high performance and low power through increased parallelism and power savings. The CPU supports an internal bus structure composed of one program bus, one 32-bit data read bus, two 16-bit data read buses, two 16-bit data write buses, and additional buses dedicated to peripheral and DMA activity. These buses provide the ability to perform up to four 16-bit data reads and two 16-bit data writes in a single cycle. The device also includes four DMA controllers, each with 4 channels that provide data movement for 16 independent channel contexts without CPU intervention. Each DMA controller can perform one 32-bit data transfer per cycle, both in parallel and independent of the CPU activity. The C55x CPU provides two multiply-and-accumulate (MAC) units, each capable of 17-bit × 17-bit multiplication and a 32-bit add in a single cycle. A central 40-bit arithmetic and logic unit (ALU) is supported by an additional 16-bit ALU. Used under instruction set control, the ALUs provide the ability to optimize parallel activity and power consumption. These resources are managed in the address unit (AU) and data unit (DU) of the C55x CPU. The C55x CPU supports a variable byte width instruction set for improved code density. The instruction unit (IU) fetches 32-bit program from internal or external memory and queues instructions for the program unit (PU). The PU decodes the instructions, directs tasks to the AU and DU resources, and manages the fully protected pipeline. Predictive branching avoids pipeline flushes when conditional instructions execute. The GPIO functions, along with the 10-bit SAR ADC, provide sufficient pins for status, interrupts, and bit I/O for LCD displays, keyboards, and media interfaces. Serial media is supported through two secure digital (SD) peripherals, four Inter-IC Sound (I2S Bus) modules, one serial port interface (SPI) with up to three chip selects, one Inter-Integrated Circuit (I2C) multimaster and slave interface, and a universal asynchronous receiver/transmitter (UART) interface. Additional peripherals include: a high-speed universal serial bus (USB 2.0) device mode only, a real-time clock (RTC), three general-purpose (GP) timers with one configurable as a watchdog timer, and an analog phase-locked loop (APLL) clock generator. In addition, the device includes a tightly coupled FFT hardware accelerator. The tightly coupled FFT hardware accelerator supports 8- to 1024-point (in power of 2) real and complex-valued FFTs. Furthermore, the device includes the following three integrated LDOs to power different sections of the device: ANA_LDO provides 1.3 V to the DSP PLL (VDDA_PLL), SAR, and power-management circuits (VDDA_ANA). DSP_LDO provides 1.3 V or 1.05 V to the DSP core (CVDD), selectable on-the-fly by software as long as operating frequency ranges are observed. USB_LDO provides 1.3 V to the USB core digital (USB_VDD1P3) and PHY circuits (USB_VDDA1P3). |
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