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TPS259271DRCT Datasheet(PDF) 3 Page - Texas Instruments |
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TPS259271DRCT Datasheet(HTML) 3 Page - Texas Instruments |
3 / 31 page GND dV/dT VIN EN/UVLO ILIM BFET OUT OUT OUT VIN VIN 1 5 6 10 TPS259270, TPS259271 www.ti.com SLVSCU8A – AUGUST 2015 – REVISED AUGUST 2015 5 Device Comparison Table PART NUMBER UV OV CLAMP FAULT RESPONSE STATUS TPS259271 4.3 V — Auto-retry Active TPS259270 4.3 V — Latched Preview 6 Pin Configuration and Functions DRC Package 10-Pin VSON Top View Pin Functions PIN DESCRIPTION NAME NUMBER Connect this pin to the gate of a blocking NFET. See the Feature Description. This pin can be left floating if BFET 9 it is not used. dV/dT 1 Connect a capacitor from this pin to GND to control the ramp rate of OUT at device turn-on. EN/UVLO 2 This is a dual function control pin. When used as an ENABLE pin and pulled down, it shuts off the internal pass MOSFET and pulls BFET to GND. When pulled high, it enables the device and BFET. As an UVLO pin, it can be used to program different UVLO trip point via external resistor divider. GND Thermal Pad GND ILIM 10 A resistor from this pin to GND will set the overload and short circuit limit. OUT 6-8 Output of the device VIN 3-5 Input supply voltage Copyright © 2015, Texas Instruments Incorporated Submit Documentation Feedback 3 Product Folder Links: TPS259270 TPS259271 |
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