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2014-10-0002

PT0480-2

11/03/14

9

PT7C4337A/4337AC

Real-time Clock Module (I

08

Alarm 1: Minutes

A1M2

*2

M40

M20

M10

M8

M4

M2

M1

09

Alarm 1: Hours

A1M3

*2

12, /24

H20 or

P, /A

H10

H8

H4

H2

H1

0A

Alarm 1: Day, Date

A1M4

*2

Day,

/Date

0,

D20

0,

D10

0,

D8

W4,

D4

W2,

D2

W1,

D1

0B

Alarm 2: Minutes

A2M2

*3

M40

M20

M10

M8

M4

M2

M1

0C

Alarm 2: Hours

A2M3

*3

12, /24

H20 or

P, /A

H10

H8

H4

H2

H1

0D

Alarm 2: Day, Date

A2M4

*3

Day,

/Date

0,

D20

0,

D10

0,

D8

W4,

D4

W2,

D2

W1,

D1

0E

Control

/ETIME

*4

0

0

RS2

*5

RS1

*5

INTCN

*6

A2IE

*7

A1IE

*7

0F

Status

OSF

*9

0

0

0

0

0

A2F

*8

A1F

*8

Caution points:

*1. PT7C4337A uses 8 bits for address. For excess 0FH address, PT7C4337A will not respond (no acknowledge signal was given).

*2. Alarm 1 mask bits. Select alarm repeated rate when an alarm occurs.

*3. Alarm 2 mask bits. Select alarm repeated rate when an alarm occurs.

*4. Oscillator and time count chain enable/disable bit.

*5. Square wave output frequency select.

*6. Interrupt output pin select bit.

*7. Alarm 1 and alarm 2 enable bits.

*8. Alarm 1 and alarm 2 flag bits.

*9. Oscillator stops flag.

*10. All bits marked with "0" are read-only bits. Their value when read is always "0".

Control and status register

Addr.

(hex)

Description

D7

D6

D5

D4

D3

D2

D1

D0

0E

Control

/ETIME

0

0

RS2

RS1

INTCN

A2IE

A1IE

(default)

0

0

0

1

1

0

0

0

0F

Status

OSF

0

0

0

0

0

A2F

A1F

(default)

1

0

0

0

0

0

Undefined

Undefined

Oscillator related bits



/ETIME

Enable oscillator and time count chain bit.

/ETIME

Data

Description

Read / Write

0

Enable oscillator and time count chain.

Default

1

Disable oscillator and time count chain.



OSF

Oscillator Stops Flag.

A logic 1 in this bit indicates that the oscillator either is stopped or was stopped for some period of time and may be used to judge

the validity of the clock and calendar data. This bit is set to logic 1 anytime that the oscillator stops. The following are examples

of conditions that can cause the OSF bit to be set:

1) The first time power is applied.

2) The voltage present on VCC is insufficient to support oscillation.

3) The /ETIME bit is turned off.

4) External influences on the crystal (e.g., noise, leakage, etc.).

This bit remains at logic 1 until written to logic 0.