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TPS65010 Datasheet(PDF) 11 Page - Texas Instruments |
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TPS65010 Datasheet(HTML) 11 Page - Texas Instruments |
11 / 63 page TPS65010 www.ti.com SLVS149C – JUNE 2003 – REVISED SEPTEMBER 2015 Battery Charger Electrical Characteristics (continued) VO(REG) + V(DO-MAX) ≤ V(CHG) = V(AC) or V(USB), I(TERM) < IO≤ 1 A, 0°C < TA< 85°C PARAMETER TEST CONDITIONS MIN TYP MAX UNIT VIL Low level input voltage 0 0.8 V VIH High level input voltage 2 VCC (5) V II Input leakage current 1 µA rDS(on) Internal NMOS VOL = 0.3 V 150 Ω LOGIC SIGNALS PG, LED2 VOL Low level output voltage IOL = 20 mA 0.5 V VOH High level output voltage 6 V VIBRATOR DRIVER VIB VOL Low level output voltage IOL = 100 mA 0.3 0.5 V VOH High level output voltage 6 V THERMAL SHUTDOWN T(SD) Thermal shutdown Increasing junction temperature 160 °C UNDERVOLTAGE LOCK OUT V(UVLO) 2.5 V -3% 3% Undervoltage lockout V(UVLO) V(UVLO) 2.75 V -3% 3% Filter resistor = 10R in series threshold with VCC, VCC decreasing V(UVLO) 3.0 V -3% 3% Default value V(UVLO) 3.25 V -3% 3% V(UVLO_HYST) UVLO comparator hysteresis VCC rising 150 200 mV POWER GOOD VMAIN, VCORE, VLDO1, VLDO2 -12% -10% -8% decreasing VMAIN, VCORE, VLDO1, VLDO2 -7% -5% -3% increasing (5) If the input voltage is higher than VCC an additional current, limited by an internal 10-kΩ resistor, flows. 6.7 Serial Interface Timing Requirements MIN MAX UNIT fMAX Clock frequency 400 kHz twH(HIGH) Clock high time 600 ns twL(LOW) Clock low time 1300 ns tR DATA and CLK rise time 300 ns tF DATA and CLK fall time 300 ns th(STA) Hold time (repeated) START condition (after this period the first clock pulse is generated) 600 ns th(DATA) Setup time for repeated START condition 600 ns th(DATA) Data input hold time 0 ns tsu(DATA) Data input setup time 100 ns tsu(STO) STOP condition setup time 600 ns t(BUF) Bus free time 1300 ns Copyright © 2003–2015, Texas Instruments Incorporated Submit Documentation Feedback 11 Product Folder Links: TPS65010 |
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