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TPS61050DRCT Datasheet(PDF) 3 Page - Texas Instruments |
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TPS61050DRCT Datasheet(HTML) 3 Page - Texas Instruments |
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3 / 49 page  TPS61050, TPS61052 www.ti.com SLUS525A – MARCH 2007 – REVISED SEPTEMBER 2015 5 Pin Configuration and Functions DRC Package YZG Package 10-Pin VSON 12-Pin DSBGA Top View Top View YZG Package 12-Pin DSBGA Bottom View Pin Functions PIN I/O DESCRIPTION NAME VSON DSBGA AVIN 5 D3 I This is the input voltage pin of the device. Connect directly to the input bypass capacitor. VOUT 9 A2 O Boost converter output. LED return input. This feedback pin regulates the LED current through the internal sense LED 6 D2 I resistor by regulating the voltage across it. The regulation operates with typically 250 mV dropout voltage. Connect to the cathode of the LED. Flash strobe pulse synchronization input. FLASH_SYNC = LOW (GND): The device is operating and regulating the LED current to the FLASH_SYNC 10 A1 I torch current level (TC). FLASH_SYNC = HIGH (VIN): The device is operating and regulating the LED current to the flash current level (FC). SCL 2 B3 I Serial interface clock line. This pin must not be left floating and must be terminated. SDA 1 A3 I/O Serial interface address/data line. This pin must not be left floating and must be terminated. General purpose input/output (refer to REGISTER2). This pin can either be configured as a GPIO 3 C3 I/O logic input or as an open-drain output (TPS61050). ENVM 3 C3 I Enable pin for voltage mode boost converter (TPS61052). Inductor connection. Drain of the internal power MOSFET. Connect to the switched side of SW 8 B1, B2 I/O the inductor. SW is high impedance during shutdown. PGND 7 C1, C2 — Power ground. Connect to AGND underneath IC. AGND 4 D1 — Analog ground. PowerPAD™ — — — Internally connected to PGND. Copyright © 2007–2015, Texas Instruments Incorporated Submit Documentation Feedback 3 Product Folder Links: TPS61050 TPS61052 |
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