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PI6LC48S04 Datasheet(PDF) 9 Page - Pericom Semiconductor Corporation |
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PI6LC48S04 Datasheet(HTML) 9 Page - Pericom Semiconductor Corporation |
9 / 11 page 9 PI6LC48S04 HiFlex Serial Interface Clock PI6LC48S04 RevA 10/12/15 Power Supply Filtering Techniques As in any high speed analog circuitry, the power supply pins are vulnerable to random noise. To achieve optimum jitter perfor- mance, power supply isolation is required. The PI6LC48S04 provides separate power supplies to isolate any high switching noise from the outputs to the internal PLL. VDD and VDDA should be individually connected to the power supply plane through vias, and 0.1μF bypass capacitors should be used for each pin. Figure below illustrates this for a generic VDD pin and also shows that VDDA requires that an additional 10Ω resistor along with a 10μF bypass capacitor be connected to the VDDA pin. VDD 0.1µF 0.1µF 10µF 10Ω * 3.3V or 2.5V VDDA * If VDD is 2.5V, the resistor value will be di erent, see app note for details 15-0128 |
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