5

www.pericom.com

PI6LC48P03A

Rev. A

6/9/2015

PI6LC48P03A

3-Output LVPECL Networking Clock Generator

Symbol

Parameter

Condition

Min

Typ

Max

Units

V

1.9

2.4

V

V

1.1

1.6

V

1.2

1.6

V

V

0.4

0.8

Note: 1. LVPECL Termination: Source 150ohm to GND and 100ohm across CLK and CLK#.

LVPECL Termination: Source 150ohm to GND and using 0.01uF ac-coupled to 50ohm to GND

Symbol

Parameter

Condition

Min.

Typ.

Max

Units

Output Frequency

NA_SEL[1:0] / NB_SEL[1:0] = 00

560

700

MHz

NA_SEL[1:0] / NB_SEL[1:0] = 01

280

350

MHz

NA_SEL[1:0] / NB_SEL[1:0] = 10

140

175

MHz

NA_SEL[1:0] / NB_SEL[1:0] = 11

112

140

MHz

Output with same VDD and load

30

ps

Output @ Same Frequencies

60

ps

Output @ Different Frequencies

75

ps

RMS Phase Jitter,

625MHz,

(1.875MHz - 20MHz)

0.15

ps

625MHz,

(12kHz - 20MHz)

0.3

ps

312.5MHz,

(1.875MHz - 20MHz)

0.15

ps

312.5MHz,

(12kHz - 20MHz)

0.3

ps

156.25MHz,

(1.875MHz - 20MHz)

0.15

ps

156.25MHz,

(12kHz - 20MHz)

0.3

ps

125MHz,

(1.875MHz - 20MHz)

0.15

ps

125MHz,

(12kHz - 20MHz)

0.3

ps

Output Rise/Fall Time

20% to 80%

400

ps

o

DC

48

52

%

Note:

1. Defined as skew within a bank of outputs at the same supply voltage and with equal load conditions.

2. Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at the differential cross points.

3. Please refer to the Phase Noise Plots.

4. This parameter is defined in accordance with JEDEC Standard 65. Measured at the differential cross points.

5. Measured at the differential cross points.

15-0119