8

www.pericom.com

PI6LC48P03

Rev. C

5/7/2015

PI6LC48P03

3-Output LVPECL Networking Clock Generator

LVCMOS to XTAL Interface

The XTAL_IN input can accept a single-ended LVCMOS signal through an AC coupling capacitor. A general interface diagram

is shown in the figure below. The XTAL_OUT pin can be left floating. The input edge rate can be as slow as 10ns. For LVCMOS

signals, it is recommended that the amplitude be reduced from full swing to half swing in order to prevent signal interference with

the power rail and to reduce noise. This configuration requires that the output impedance of the driver (Ro) plus the series resis-

tance (Rs) equals the transmission line impedance. In addition, matched termination at the crystal input will attenuate the signal in

half. This can be done in one of the two ways. First, R1 and R2 in parallel should equal the transmission line empedance. For most

50Ω applications, R1 and R2 can be 100Ω. This can also be accomplished by removing R1 and making R2 50Ω. By overdriving the

crystal oscillator, the device will be functional, but note, the device performance is quaranteed by using a quartz crystal.

V

R2

50Ω

DD

Ro

Rs

Zo = Ro + Rs

R1

XTAL_IN

XTAL_OUT

0.1µF

15-0059