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PI6CFGL401BZHIE Datasheet(PDF) 10 Page - Pericom Semiconductor Corporation |
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PI6CFGL401BZHIE Datasheet(HTML) 10 Page - Pericom Semiconductor Corporation |
10 / 14 page 10 www.pericom.com 06/05/15 All trademarks are property of their respective owners. PI6CFGL401B 4-Output Low Power PCIE Gen 1-2-3 Clock Generator SMBus Table: Output Enable Register BYTE 0 Bit Name Control Function Type 0 1 Default 7 Reserved 1 6 Reserved 1 5 Reserved 1 4 Reserved 1 3 OE3 Output Enable RW Low Enabled 1 2 OE3 Output Enable RW Low Enabled 1 1 OE2 Output Enable RW Low Enabled 1 0 OE0 Output Enable RW Low Enabled 1 SMBus Table: SS Readback and Vhigh Control Register BYTE 1 Bit Name Control Function Type 0 1 Default 7 SSENRB1 SS Enable Readback Bit1 R 00' for SS_EN_tri = 0, '01' for SS_EN_tri = 'M', '11 for SS_EN_tri = '1' Latch 6 SSENRB0 SS Enable Readback Bit0 R Latch 5 SSEN_SWCNTRL Enable SW control of SS RW SS control locked Values in B1[4:3] control SS amount. 0 4 SSENSW1 SS Enable Software Ctl Bit1 RW1 00' = SS Off, '01' = -0.25% SS, '10' = Reserved, '11'= -0.5% SS 0 3 SSENSW0 SS Enable Software Ctl Bit0 RW1 0 2 Reserved 1 1 AMPLITUDE 1 Controls Output Amplitude RW 00 = 0.6V 01 = 0.7V 1 0 AMPLITUDE 0 RW 10= 0.8V 11 = 0.9V 0 1. B1[5] must be set to a 1 for these bits to have any effect on the part. SMBus Table: CLK Slew Rate Control Register BYTE 2 Bit Name Control Function Type 0 1 Default 7 Reserved 1 6 Reserved 1 5 Reserved 1 4 Reserved 1 3 SLEWRATESEL CLK3 Adjust Slew Rate of CLK3 RW 2.0V/ns 3.0V/ns 1 2 SLEWRATESEL CLK2 Adjust Slew Rate of CLK2 RW 2.0V/ns 3.0V/ns 1 1 SLEWRATESEL CLK1 Adjust Slew Rate of CLK1 RW 2.0V/ns 3.0V/ns 1 0 SLEWRATESEL CLK0 Adjust Slew Rate of CLK0 RW 2.0V/ns 3.0V/ns 1 15-0072 |
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