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03/03/15

PI6CFGL202B

Low Power PCIe 3.0 Clock Generator with 2 HCSL Outputs

Symbol

Parameters

Condition

Min. Typ.

Max. Units

f

MODIN

Input SS Modulation

Allowable Frequency

(Triangular Modulation)

30

31.500 33

kHz

All output

10

μs

All output

10

μs

From Power-up to

3.0

ms

Setting period after

Setting period after spread change

3.0

ms

Note:

1. Guaranteed by design and characterization, not 100% tested in production.

2. Control input must be monotonic from 20% to 80% of input swing. Input Frequency Capacitance

3. Time from deassertion until outputs are >200 mV

4. DIF_IN input

o

C; VDD = 3.3V+/-

10%; VDDO = 1.8V+/-10%, See Test Loads for Loading Conditions)

Symbol

Parameters

Condition

Min.

Typ. Max.

Units

Trf

1.1

2

4.5

V/ns

V

HIGH

Statistical measurement on single-ended signal

using oscilloscope math function. (Scope averag-

ing on)

660

950

mV

V

LOW

-150

150

mV

Vmax

Measurement on single ended signal using

absolute value. (Scope averaging off)

1150

mV

Vmin

-300

mV

Vswing

Scope averaging off

300

mV

Vcross_abs

Scope averaging off

250

550

mV

Δ-Vcross

Scope averaging off

140

mV

t

DC

Measured differentially, PLL Mode

45

55

%

t

skew

50

ps

t

jcyc-cyc

PLL mode @100MHz output, SSC off

50

ps

Note:

1. Guaranteed by design and characterization, not 100% tested in production.

2. Measured from differential waveform

3. Slew rate is measured through the Vswing voltage range centered around differential 0V. This results in a +/-150mV window around differential 0V.

4. Matching applies to rising edge rate for Clock and falling edge rate for Clock#. It is measured using a +/-75mV window centered on the average cross point

where Clock rising meets Clock# falling. The median cross point is used to calculate the voltage thresholds the oscilloscope is to use for the edge rate calcula-

tions.

5. Vcross is defined as voltage where Clock = Clock# measured on a component test board and only applies to the differential rising edge (i.e. Clock rising and

Clock# falling).

6. The total variation of all Vcross measurements in any particular system. Note that this is a subset of Vcross_min/max (Vcross absolute) allowed. The intent is

to limit Vcross induced modulation by setting Δ-Vcross to be smaller than Vcross absolute.

15-0025