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PI6C49X0210-A Datasheet(PDF) 8 Page - Pericom Semiconductor Corporation

Part # PI6C49X0210-A
Description  High Performance 1:10 Multi-Voltage CMOS Buffer
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Manufacturer  PERICOM [Pericom Semiconductor Corporation]
Direct Link  http://www.pericom.com
Logo PERICOM - Pericom Semiconductor Corporation

PI6C49X0210-A Datasheet(HTML) 8 Page - Pericom Semiconductor Corporation

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PI6C49X0210-A
High Performance 1:10 Multi-Voltage CMOS Buffer
www.pericom.com
PI6C49X0210-A Rev A 01/17/14
Storage Temperature...........................................................–65°C to +150°C
VDD, VDDO Voltage...............................................................–0.5V to +3.6V
Output Voltage (max. 4.6V) .......................................... –0.5V to VDD+0.5V
Input Voltage (max 4.6V).............................................. –0.5V to VDD+0.5V
2.5V Absolute Maximum Ratings (Above which the useful life may be impaired. For user guidelines only, not tested.)
Note:
Stresses greater than those listed under MAXIMUM
RATINGS may cause permanent damage to the
device. This is a stress rating only and functional operation
of the device at these or any other conditions above those
indicated in the operational sections of this specification is
not implied. Exposure to absolute maximum rating condi-
tions for extended periods may affect reliability.
AC Characteristics (Over Operating Range: VDD/VDDO = 2.5V ± 5%, TA = -40° to 85°C)
Parameters
Description
Test Conditions(1)
Min.
Typ
Max.
Units
fMAX
Output Frequency
Using External Crystal
10
50
MHz
Using External Clock
Source (2)
DC
200
odc
Output Duty Cycle
125MHz
45
55
%
tsk(o)
Output Skew (3)
80
ps
tjit(Ø)
RMS Phase Jitter (Random)
25MHz @ (Integra-
tion Range: 100Hz-
1MHz)
0.2
ps
tjit(additive)
Additive RMS Phase Jitter (Random)
125MHz @ (Integra-
tion Range: 12kHz-
20MHz)
0.05
ps
tR/tF
Output Rise/Fall Time
20% to 80%
200
800
ps
tEN
Output Enable Time
(4)
ENABLE
5
cycles
tDIS
Output Disable Time
(4)
ENABLE
5
cycles
MUXisolation
MUX Isolation
155.52MHz
63
dB
Notes:
1. Unless noted otherwise, all parameters are tested with xtal @ f <= Fxtal_max,; outputs are terminated @ 50Ω to
VDDO/2, see waveforms.
2. Diff external clock source is driving IN0/IN0# and IN1/IN1# input. IN0/IN1 can be single end ref clock when IN0# /IN1# set as VDD/2
3. Identical conditions: loading, transitions, supply voltage, temperature, package type and speed grade.
4. These parameters are guaranteed, but not tested. Max delay is 4 cycles. Min. setup time = 3ns.
14-0008


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