4

5

6

7

8

11

12

PBI

VC2

VC1

SRN

SRP

VSS

TS 1

SCL

SDA

PACK

3

2

1

9

10

CHG

DSG

3

bq28z610

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SLUSAS3B – APRIL 2014 – REVISED DECEMBER 2015

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P = Power Connection, O = Digital Output, AI = Analog Input, I = Digital Input, I/O = Digital Input/Output

6 Pin Configuration and Functions

Pin Functions

PIN

DESCRIPTION

NAME

DRZ

VSS

1

P

Device ground

SRN

2

AI

Analog input pin connected to the internal coulomb counter peripheral for integrating a small

voltage between SRP and SRN where SRP is the top of the sense resistor.

SRP

3

AI

Analog input pin connected to the internal coulomb counter peripheral for integrating a small

voltage between SRP and SRN where SRP is the top of the sense resistor.

TS1

4

AI

Temperature input for ADC to the oversampled ADC channel, and optional Battery Trip Point

(BTP) output

SCL

5

I/O

SDA

6

I/O

DSG

7

O

N-CH FET drive output pin

PACK

8

AI, P

Pack sense input pin

CHG

9

O

N-CH FET drive output pin

PBI

10

P

Power supply backup input pin

VC2

11

AI, P

Sense voltage input pin for most positive cell, balance current input for most positive cell. Primary

power supply input and battery stack measurement input (BAT)

VC1

12

AI

Sense voltage input pin for least positive cell, balance current input for least positive cell

PWPD

—

Exposed Pad, electrically connected to VSS (external trace)