TPS650860A0RSKR datasheet(7/94 Pages) TI1

Part #	TPS650860A0RSKR

Description	Configurable Multirail PMU for Multicore Processors

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Manufacturer	TI1 [Texas Instruments]

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TPS650860

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SWCS128A – MARCH 2015 – REVISED DECEMBER 2015

Pin Functions (continued)

NO.

NAME

I/O

DESCRIPTION

INTERFACE

Active-high VR enable pin. A group of VRs can be assigned to be enabled at assertion or

13

CTL1

I

disabled at deassertion of this pin.

Active-high VR enable pin. A group of VRs can be assigned to be enabled at assertion or

disabled at deassertion of this pin. Alternatively, when configured to active-low sleep enable, a

14

CTL6/SLPENB2

I

group of VRs chosen can be entered into (L) or out of (H) sleep state where their output

voltages may be different from those in normal state.

15

IRQB

O

Open-drain output interrupt pin. Refer to Section 5.9.3 for definitions.

General purpose output that can be configured to either open-drain or push-pull arrangement.

Regardless of the configuration, the pin can be programmed either to reflect power good status

16

GPO1

O

of VRs of any choice or to be controlled by an I2C register bit by the user, which then can be

used as an enable signal to an external VR.

General purpose output that can be configured to either open-drain or push-pull arrangement.

Regardless of the configuration, the pin can be programmed either to reflect power good status

26

GPO2

O

of VRs of any choice or to be controlled by an I2C register bit by the user, which then can be

used as an enable signal to an external VR.

General purpose output that can be configured to either open-drain or push-pull arrangement.

Regardless of the configuration, the pin can be programmed either to reflect power good status

27

GPO3

O

of VRs of any choice or to be controlled by an I2C register bit by the user, which then can be

used as an enable signal to an external VR.

Open-drain output that can be configured to reflect power good status of VRs of any choice or

28

GPO4

O

to be controlled by an I2C register bit by the user, which then can be used as an enable signal

to an external VR.

58

CLK

I

I2C clock

59

DATA

I/O

I2C data

Active-high VR enable pin. A group of VRs can be assigned to be enabled at assertion or

60

CTL2

I

disabled at deassertion of this pin.

Active-high VR enable pin. A group of VRs can be assigned to be enabled at assertion or

disabled at deassertion of this pin. Alternatively, when configured to active-low sleep enable, a

61

CTL3/SLPENB1

I

group of VRs chosen can be entered into (L) or out of (H) sleep state where their output

voltages may be different from those in normal state.

Active-high VR enable pin. A group of VRs can be assigned to be enabled at assertion or

62

CTL4

I

disabled at deassertion of this pin.

Active-high VR enable pin. A group of VRs can be assigned to be enabled at assertion or

63

CTL5

I

disabled at deassertion of this pin.

REFERENCE

Band-gap reference output. Stabilize it by connecting a 100-nF (TYP) ceramic capacitor

53

VREF

O

between this pin and quiet ground.

Analog ground. Do not connect to the thermal pad ground on top layer. Connect to ground of

52

AGND

—

VREF capacitor.

System voltage detection and input to internal LDOs (3.3 V and 5 V). Bypass to ground with a

55

VSYS

I

1-µF (TYP) ceramic capacitor.

THERMAL PAD

Thermal pad

—

Connect to PCB ground plane using multiple vias for good thermal and electrical performance.

Pin Configuration and Functions

7

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