Receiver, High IIP3, SMD

40.5 - 43.5 GHz

Rev. V2

MADC-010736

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voltages available and the power dissipation constraints, the bias circuits may include a single transistor or a low

power operational amplifier, with a low value resistor in series with the drain supply to sense the current. Make

sure to sequence the applied voltage to ensure negative gate bias is available before applying the positive drain

supply.

App Note [2] I/Q - For highest gain, best image rejection and lowest noise figure all 4 IF ports should be used. I/

I* and Q/Q* will combine through two 180 degree hybrid couplers generating inphase and quadrature phase

components. Inphase and quadrature signals then need to be combined through 90 degree hybrid combiner to

create IF output.

App Note [3] Board Layout - It is recommended to provide 100 pF decoupling capacitors as close to the bias

pins as possible. Additional 10 nF and 1 µF on each of the bias lines are recommended placed a distance

further away.

90 deg Hybrid

IF Output

Q*

Q

I

I*

VG4

RF

VD2

VG2

VD1

VG1

VD3

VG3

LO

1

2

3

4

5

6

7

13

12

11

10

9

8

Q*

Q

I

I*

IRM

LNA

BUF

BUF 2X

180 deg Hybrid

180 deg Hybrid