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BQ76PL455ATPFCRQ1 Datasheet(PDF) 2 Page - Texas Instruments |
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BQ76PL455ATPFCRQ1 Datasheet(HTML) 2 Page - Texas Instruments |
2 / 130 page 2 bq76PL455A-Q1 SLUSC51B – APRIL 2015 – REVISED DECEMBER 2015 www.ti.com Product Folder Links: bq76PL455A-Q1 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated Table of Contents 1 Features .................................................................. 1 2 Applications ........................................................... 1 3 Description ............................................................. 1 4 Revision History..................................................... 2 5 Pin Configuration and Functions ......................... 3 6 Specifications......................................................... 7 6.1 Absolute Maximum Ratings ...................................... 7 6.2 ESD Ratings ............................................................ 7 6.3 Recommended Operating Conditions ....................... 8 6.4 Thermal Information .................................................. 8 6.5 Electrical Characteristics: Supply Current................. 8 6.6 VP 5.3-V Supply Regulation Voltage ........................ 9 6.7 VDD18 1.8-V Internal Digital Supply......................... 9 6.8 V5VAO Analog Supply .............................................. 9 6.9 VM –5-V Integrated Charge Pump .......................... 9 6.10 Analog-to-Digital Converter (ADC): Analog Front End............................................................................. 9 6.11 ADC: VSENSEn Cell Measurement Inputs........... 10 6.12 ADC: VMODULE Input.............................................. 10 6.13 ADC: Post Board Assembly(6): VSENSEn Cell Measurement Inputs ................................................ 11 6.14 ADC: AUXn General Purpose Inputs .................... 11 6.15 ADC: Internal Temperature Measurement and Thermal Shutdown (TSD) ........................................ 12 6.16 Passive Balancing Control Outputs ...................... 12 6.17 Digital Input/Output: VIO-Based Single-Ended I/O ............................................................................ 12 6.18 Digital Input/Output: Daisy Chain Vertical Bus ..... 13 6.19 Digital Input/Output: Wakeup ................................ 13 6.20 EEPROM............................................................... 13 6.21 Secondary Protector – Window Comparators ..... 13 6.22 Power-On-Reset (POR) and FAULT Flag Thresholds ............................................................... 14 6.23 Miscellaneous ....................................................... 14 6.24 Typical Characteristics .......................................... 15 7 Detailed Description ............................................ 17 7.1 Overview ................................................................. 17 7.2 Functional Block Diagram ....................................... 18 7.3 Feature Description................................................. 18 7.4 Device Functional Modes........................................ 45 7.5 Command and Response Protocol ......................... 49 7.6 Register Maps ......................................................... 64 8 Application and Implementation ........................ 98 8.1 Application Information............................................ 98 8.2 Typical Application ................................................ 110 8.3 Initialization Set Up .............................................. 115 9 Power Supply Recommendations .................... 117 9.1 NPN LDO Supply .................................................. 117 10 Layout................................................................. 119 10.1 Layout Guidelines ............................................... 119 10.2 Layout Example .................................................. 119 10.3 Board Construction and Accuracy ...................... 120 11 Device and Documentation Support ............... 122 11.1 Device Support .................................................. 122 11.2 Documentation Support ..................................... 123 11.3 Community Resources........................................ 123 11.4 Trademarks ......................................................... 123 11.5 Electrostatic Discharge Caution .......................... 123 11.6 Glossary .............................................................. 123 12 Mechanical, Packaging, and Orderable Information ......................................................... 124 4 Revision History NOTE: Page numbers for previous revisions may differ from page numbers in the current version. Changes from Revision A (September 2015) to Revision B Page • Updated the Features list ....................................................................................................................................................... 1 • Change paragraph 3 of the Description ................................................................................................................................ 1 Changes from Original (April 2015) to Revision A Page • Updated VCHERR25NB and VCHERR values, deleted Note 3 in the ADC: VSENSEn Cell Measurement Inputs table ..................................................................................................................................................................................... 10 • Changed the Test Conditions for VCOMP_REF_45 in the Secondary Protector – Window Comparators table, From: Measured by ADC To: Measured by ADC as HREF - HREF_GND ................................................................................... 14 • Changed VDD18, First Sample From: "CMD_OVS_GPER" To: "Approximately 30 µs" in Table 2 ................................... 25 • Deleted TSD (DIG) row and Note 4 from Table 3 ............................................................................................................... 25 • Changed text From: "Allowing for the lowest possible module voltage (VBAT min) of 16 V" To: "Allowing for the lowest possible module voltage (VBAT min) of 12 V" in the NPN LDO Supply section....................................................... 117 • Added section Board Construction and Accuracy ............................................................................................................. 120 |
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