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TB67S103AFTG Datasheet(PDF) 2 Page - Toshiba Semiconductor |
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TB67S103AFTG Datasheet(HTML) 2 Page - Toshiba Semiconductor |
2 / 39 page TB67S103AFTG/FNG 2014-01-27 2 Pin assignment (TB67S103A) Please mount the four corner pins of the QFN package and the exposed pad to the GND area of the PCB. Please mount the exposed pad of the HTSSOP package to the GND area of the PCB. 1 2 3 4 5 6 7 15 16 17 18 19 20 28 29 30 31 32 33 34 42 43 44 45 46 47 48 21 OSCM SCLK SO SDATA SSET NC NC NC OUTA+ OUTA+ NC NC GND NC GND NC NC NC OUTB+ OUTB+ NC NC VREFB ID VREFA LO GND NC FNG (Top View) 22 23 24 25 26 27 8 9 10 11 12 13 14 35 36 37 38 39 40 41 CLK ENABLE RESET GND NC RSA RSA OUTA- OUTA- GND GND OUTB- OUTB- NC RSB RSB VM NC VCC NC (Top View) 1 2 3 4 5 6 7 8 9 10 11 12 36 35 34 33 32 31 30 29 28 27 26 13 14 15 16 17 18 19 20 21 22 23 24 25 48 47 46 45 44 43 42 41 40 39 38 37 FTG NC NC GND OUTA- OUTA- GND GND OUTB- OUTB- GND NC NC NC LO ID GND VREFB VREFA OSCM SCLK SO SDATA SSET NC |
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