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SP791CP Datasheet(PDF) 9 Page - Sipex Corporation |
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SP791CP Datasheet(HTML) 9 Page - Sipex Corporation |
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9 / 19 page  9 SP791DS/08 SP791 Low Power Microprocessor Supervisory with Battery Switch-Over © Copyright 2000 Sipex Corporation MR low for a minimum of 25 µs resets all the internal counters, sets the Watchdog Output (WDO) and Watchdog-Pulse Output (WDPO) high, and sets the Set Watchdog-Timeout (SWT) input to VOUT if it is not already connected to VOUT (for Internal timeouts). It also, disables the Chip-Enable Output (CE OUT) forcing it to a high state. The RESET output remains at a logic low as long as MR is held low, and the reset-timeout period begins after MR returns high, Figure 2. Use this input as either a digital-logic input or a second low-line comparator. Normal TTL/ CMOS levels can be wire-OR connected via pull-down diodes, Figure 3, and open-drain/col- lector outputs can be wire-ORed directly. RESET OUTPUT The SP791's RESET output ensures that the µP powers up in a known state, and prevents code- execution errors during power-down or brown- out conditions. The RESET output is active low, and typically sinks 3.2mA at 0.1V saturation voltage in its active state. When deasserted, RESET sources 1.6mA at VOUT – 0.5V. When no backup bat- tery is used, RESET output is valid down to VCC = 1V, and an external 10k Ω pull-down resistor on RESET ensures that RESET will be valid with VCC down to GND as shown on Figure 4. As VCC goes below 1V, the gate drive to the RESET output switch reduces accordingly, increasing the r DS(ON) and the saturation volt- age. The 10k Ω pull-down resistor ensures the parallel combination of switch and external resistor is 10k Ω and the output saturation volt- age is below 0.4V, while sinking 40 µA. When using a 10k Ω external pull-down resistor, the high state for the RESET output with Vcc = 4.75V is 4.5V typical. For battery voltages greater than or equal to 2V, RESET remains valid for VCC between 0V and 5.5V. RESET will be asserted during the following conditions: 1) VCC < 4.65V (typ) 2) MR < 1.25V (typ) 3) RESET = logic "0" ; for 200 ms (typ) after Vcc rises above 4.65V or after MR has exceeded 1.25V. The SP791 battery-switchover comparator does not affect RESET assertion. Figure 5. WDI, WDO and WDPO Timing Diagram (VCC mode). Figure 4. Adding an external pull-down resistor ensures RESET is valid with VCC down to GND. Figure 6. Two consecutive watchdog faults latch the system in reset. TO µP RESET 10k 15 Corporation RESET 1.6sec 100ns MIN WDI WDPO WDO 70ns Corporation Vcc VBATT VOUT RESET WDI LOWLINE WDPO WDO GND MR 3.6V 1 3 2 15 11 10 16 14 9 4.7k Ω *1 µF +5V REACTIVATE 4 CLOCK D SET Vcc CD4013 RESET Vss Q Q 2 1 14 3 6 5 4 7 1/6 74HC04 TWO CONSECUTIVE WATCHDOG FAULT INDICATIONS µP POWER µP RESET I/O NMI INTERRUPT 0.1 µF +5V ∗ SETS Q HIGH ON POWER-UP |
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