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TPS65632RTER Datasheet(PDF) 10 Page - Texas Instruments |
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TPS65632RTER Datasheet(HTML) 10 Page - Texas Instruments |
10 / 28 page TPS65632 SLVSCY2A – MARCH 2015 – REVISED JANUARY 2016 www.ti.com Feature Description (continued) Table 1. Bit / Rising Edges VNEG DAC Value Bit / Rising Edges VNEG DAC Value 0 / no pulse –4.0 V 000000 21 –3.4 V 010101 1 –5.4 V 000001 22 –3.3 V 010110 2 –5.3 V 000010 23 –3.2 V 010111 3 –5.2 V 000011 24 –3.1 V 011000 4 –5.1 V 000100 25 –3.0 V 011001 5 –5.0 V 000101 26 –2.9 V 011010 6 –4.9 V 000110 27 –2.8 V 011011 7 –4.8 V 000111 28 –2.7 V 011100 8 –4.7 V 001000 29 –2.6 V 011101 9 –4.6 V 001001 30 –2.5 V 011110 10 –4.5 V 001010 31 –2.4 V 011111 11 –4.4 V 001011 32 –2.3 V 100000 12 –4.3 V 001100 33 –2.2 V 100001 13 –4.2 V 001101 34 –2.1 V 100010 14 –4.1 V 001110 35 –2.0 V 100011 15 –4.0 V 001111 36 –1.9 V 100100 16 –3.9 V 010000 37 –1.8 V 100101 17 –3.8 V 010001 38 –1.7 V 100110 18 –3.7 V 010010 39 –1.6 V 100111 19 –3.6 V 010011 40 –1.5 V 101000 20 –3.5 V 010100 41 –1.4 V 101001 7.3.2.2 Controlling VNEG Transition Time The transition time (tSET) is the time required to move VNEG from one voltage level to the next. Users can control the transition time with a capacitor connected between the CT pin and ground. When the CT pin is left open or connected to ground the transition time is as short as possible. When a capacitor is connected to the CT pin the transition time is determined by the time constant ( τ) of the external capacitor (C(CT)) and the internal resistance of the CT pin (RCT). The output voltage reaches 70% of its programmed value after 1τ. An example is given when using 100 nF for C(CT). τ = 300 kΩ × 100 nF = 30 ms (1) The output voltage is at 70% of its final value after 1 τ (i.e. 30 ms in this case) and at its final value after approximately 3 τ (90 ms in this case). 7.3.3 Boost Converter 2 (AVDD) Boost converter 2 uses a fixed-frequency current-mode topology. The TPS65632 device supports fixed output voltages of 5.8 V and 7.7 V, selected by the SELP2 pin. AVDD = 7.7 V when SELP2 is low or left floating, and AVDD = 5.8 V when SELP2 is high. 7.3.4 Soft Start and Start-Up Sequence The devices feature a soft-start function to limit inrush current. Boost converter 2 (AVDD) is enabled when EN goes high. When CTRL goes high, boost converter 1 starts with a reduced switch current limit and 10 ms later the inverting buck-boost converter (VNEG) starts with its default value of –4 V. The typical start-up sequence is shown in Figure 6. The two boost converters operate independently and boost converter 1 (VPOS) does not require boost converter 2 (AVDD) to be in regulation in order for it to start.. 10 Submit Documentation Feedback Copyright © 2015–2016, Texas Instruments Incorporated |
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