SP211EEA datasheet(5/16 Pages) SIPEX

Part #	SP211EEA

Description	5V High Performance RS232 Transceivers

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Manufacturer	SIPEX [Sipex Corporation]

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5

SP207EDS/09

SP207E Series High Performance Transceivers

FEATURES

As in the original RS-232 multi-channel

products, the SP207E Series multi–channel

RS-232 line transceivers provide a variety of

configurations to fit most communication

needs, especially those applications where +12V

is not available. All models in this Series feature

low–power CMOS construction and SIPEX–

proprietary on-board charge pump circuitry to

generate the +10V RS-232 voltage levels. The

ability to use 0.1

µF charge pump capacitors

saves board space and reduces circuit cost.

Different models within the Series provide

different driver/receiver combinations to

match any application requirement.

The SP211 and SP213E models feature a low–

power shutdown mode, which reduces power

supply drain to 1

µA. The SP213E includes a

Wake-Up function which keeps two receivers

active in the shutdown mode, unless disabled by

the EN pin.

The family is available in 28–pin SO (wide) and

SSOP (shrink) small outline packages. Devices

can be specified for commercial (0

°C to +70°C)

and industrial/extended (–40

°C to +85°C)

operating temperatures.

THEORY OF OPERATION

The SP207E Series devices are made up of

three basic circuit blocks — 1) transmitter/

driver, 2) receiver and 3) the SIPEX–

proprietary charge pump. Each model within

the Series incorporates variations of these

circuits to achieve the desired configuration

and performance.

Charge–Pump

The charge pump is a Sipex–patented design

(5,306,954) and uses a unique approach

compared to older less–efficient designs. The

charge pump still requires four external capacitors,

but uses a four–phase voltage shifting technique

to attain symmetrical 10V power supplies.

Figure 3a shows the waveform found on the

positive side of capcitor C

2, and Figure 3b

shows the negative side of capcitor C

2. There is

a free–running oscillator that controls the four

phases of the voltage shifting. A description of

each phase follows.

Phase 1

— V

SS charge storage —During this phase of the

clock cycle, the positive side of capacitors C

1

and C

2 are initially charged to +5V. Cl

+ is then

switched to ground and the charge in C

1

– is

transferred to C

2

–. Since C

2

+ is connected to

+5V, the voltage potential across capacitor C

2 is

now 10V.

Phase 2

— V

SS transfer — Phase two of the clock

connects the negative terminal of C

2 to the VSS

storage capacitor and the positive terminal of C

2

to ground, and transfers the generated –l0V to

C

3.

Simultaneously, the positive side of

capacitor C

1 is switched to +5V and the negative

side is connected to ground.

Phase 3

— V

DD charge storage — The third phase of the

clock is identical to the first phase — the charge

transferred in C

1 produces –5V in the negative

terminal of C

1, which is applied to the negative

side of capacitor C

2. Since C2

+ is at +5V, the

voltage potential across C

2 is l0V.

VCC = +5V

–5V

+5V

VSS Storage Capacitor

VDD Storage Capacitor

C1

C2

C3

C4

+

++

–

Figure 1. Charge Pump — Phase 1

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