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DM54LS169A Datasheet(PDF) 3 Page - National Semiconductor (TI) |
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DM54LS169A Datasheet(HTML) 3 Page - National Semiconductor (TI) |
3 / 8 page Switching Characteristics at VCC e 5V and TA e 25 C (See Section 1 for Test Waveforms and Output Load) From (Input) RL e 2kX Symbol Parameter To (Output) CL e 15 pF CL e 50 pF Units Min Max Min Max fMAX Maximum Clock 25 20 MHz Frequency tPLH Propagation Delay Time Clock to 35 39 ns Low to High Level Output Ripple Carry tPHL Propagation Delay Time Clock to 35 44 ns High to Low Level Output Ripple Carry tPLH Propagation Delay Time Clock to 20 24 ns Low to High Level Output Any Q tPHL Propagation Delay Time Clock to 23 32 ns High to Low Level Output Any Q tPLH Propagation Delay Time Enable T to 18 24 ns Low to High Level Output Ripple Carry tPHL Propagation Delay Time Enable T to 18 28 ns High to Low Level Output Ripple Carry tPLH Propagation Delay Time UpDown to 25 30 ns Low to High Level Output Ripple Carry (Note 1) tPHL Propagation Delay Time UpDown to 29 38 ns High to Low Level Output Ripple Carry (Note 1) Note 1 The propagation delay from UPDOWN to RIPPLE CARRY must be measured with the counter at either a minimum or a maximum count As the logic level of the updown input is changed the ripple carry output will follow If the count is minimum the ripple carry output transition will be in phase If the count is maximum the ripple carry output will be out of phase 3 |
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