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11

TPS62480

www.ti.com

SLVSCL9A – FEBRUARY 2016 – REVISED FEBRUARY 2016

Product Folder Links: TPS62480

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Copyright © 2016, Texas Instruments Incorporated

Device Functional Modes (continued)

7.4.3 Minimum Duty Cycle and 100% Mode Operation

The minimum on-time, which is typically 70ns, normally determines a limit on the minimum operating duty cycle.

The calculation is:

space

(2)

space

However, a frequency foldback lowers the switching frequency depending on the duty cycle and ensures proper

regulation for every duty cycle.

There is no limit towards maximum duty cycle. When the input voltage becomes close to the output voltage, the

device enters automatically 100% duty cycle mode and both high-side FETs switch on as long as VOUT remains

below the regulation setpoint. In this case, the voltage drop across the high-side FETs and the inductors

determines the output voltage level. An estimate for the minimum input voltage to maintain output voltage

regulation is:

space

(3)

space

In 100% duty cycle mode, the low-side FETs are switched off. The typical quiescent current in 100% mode is

3.5 mA.

7.4.4 Phase Shifted Operation

Using an inherent benefit of the two-phase conversion, the two phases of TPS6248X run out of phase. For every

switching cycle, the second phase is not allowed to turn on its high-side FET until the master phase has reached

its peak current value. This limits the input RMS current and corresponding switching noise.

7.4.5 Phase Add/Shed and Current Balancing

When the load current is below the internal threshold, only the master phase operates. The second phase

activates, if the load current exceeds the threshold of typically 1.7 A. The second phase powers off with a

hysteresis of about 0.5 A, when the load current decreases.

Since the internal circuitry and layout matches both phase circuits, the peak currents balance with less than 15%

deviation at heavy loads. This is independent of the inductor's tolerance. However, the maximum peak current,

specified as High-Side MOSFET Current Limit in Electrical Characteristics is not exceeded at any time. A

detailed example about current balancing is given in Figure 28.

7.4.6 Current Limit and Short Circuit Protection

Each phase has a separate integrated peak current limit. The dc values are specified in the Electrical

Characteristics. While its minimum value limits the output current of the phase, the maximum number gives the

current that must be considered to flow in some operating case. At the peak current limit, the device provides its

maximum output current.

However, if the current limit situation remains for 512 consecutive switching cycles, the peak current folds back to

about 1/3 of the regular limit. This limits the output power for over current and short circuit events. The foldback

current limit is released to the normal one only if the load current has decreased as far as needed to undercut

the (foldback) peak current limit.