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TPS720-Q1

SBVS278 – FEBRUARY 2016

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Copyright © 2016, Texas Instruments Incorporated

(1)

JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.

(2)

JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

6.2 ESD Ratings

VALUE

UNIT

Electrostatic discharge

±2000

V

±500

Machine model (MM)

±100

(1)

Whichever is less.

(2)

Whichever is greater.

(3)

Maximum ESR must be less than 250 m

Ω.

6.3 Recommended Operating Conditions

over operating junction temperature range (unless otherwise noted)

MIN

NOM

MAX

UNIT

Input voltage (steady-state)

1.1

(1)

V

Bias voltage

(2)

5.5

V

Output voltage

0.9

3.0

V

Peak output current

0

350

mA

Enable voltage

0

5.5

V

Input capacitance

1

µF

Bias capacitance

0.1

µF

(3)

Output capacitance

2.2

µF

(1)

For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application

report, SPRA953.

6.4 Thermal Information

TPS720-Q1

UNIT

DRV (WSON)

6 PINS

Junction-to-ambient thermal resistance

66.5

°C/W

Junction-to-case (top) thermal resistance

86.2

°C/W

Junction-to-board thermal resistance

36.1

°C/W

Junction-to-top characterization parameter

1.7

°C/W

Junction-to-board characterization parameter

36.6

°C/W

Junction-to-case (bottom) thermal resistance

7.4

°C/W