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TPS7A6050QKVURQ1 Datasheet(PDF) 5 Page - Texas Instruments |
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TPS7A6050QKVURQ1 Datasheet(HTML) 5 Page - Texas Instruments |
5 / 34 page 5 TPS7A6033-Q1, TPS7A6050-Q1 TPS7A6133-Q1, TPS7A6150-Q1 www.ti.com SLVSA62H – MARCH 2010 – REVISED MARCH 2016 Product Folder Links: TPS7A6033-Q1 TPS7A6050-Q1 TPS7A6150-Q1 Submit Documentation Feedback Copyright © 2010–2016, Texas Instruments Incorporated (1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. (2) Absolute maximum voltage for duration less than 480 ms 7 Specifications 7.1 Absolute Maximum Ratings over operating free-air temperature range (unless otherwise noted) (1) MIN MAX UNIT Unregulated inputs(2) VIN, ENABLE –0.3 45 V Regulated output VOUT –0.3 7 V Open-drain reset output nRST –0.3 7 V Output to charge an external capacitor RDELAY –0.3 7 V Operating ambient temperature, TJ –40 150 °C Storage temperature, Tstg –65 150 °C (1) AEC Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification. 7.2 ESD Ratings VALUE UNIT TPS7A60xx-Q1 and TPS7A61xx-Q1 Devices in KVU Package V(ESD) Electrostatic discharge Human-body model (HBM), per AEC Q100-002(1) ±4000 V Charged-device model (CDM), per AEC Q100-011 ±1000 TPS7A60xx-Q1 Device in KTT Package V(ESD) Electrostatic discharge Human-body model (HBM), per AEC Q100-002(1) ±4000 V Charged-device model (CDM), per AEC Q100-011 ±1500 (1) Applicable for TPS7A61xx-Q1 only. (2) Applicable for TPS7A60xx-Q1 only. 7.3 Recommended Operating Conditions over operating ambient temperature range (unless otherwise noted) MIN MAX UNIT VIN, VENABLE (1) Unregulated input voltage 4 40 V VnRST, VRDELAY (2) Low-voltage output range 0 5.25 V IOUT Output current 0 300 mA TA Operating ambient temperature –40 150 °C (1) The thermal data is based on JEDEC standard high K profile JESD 51-5. The copper pad is soldered to the thermal land pattern. The correct attachment procedure must be incorporated. (2) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report, SPRA953. 7.4 Thermal Information THERMAL METRIC(1)(2) TPS7A60xx-Q1, TPS7A61xx-Q1 TPS7A60xx-Q1 UNIT KVU (TO-252) KTT (TO-263) 5 PINS 5 PINS RθJA Junction-to-ambient thermal resistance 26.9 24.7 °C/W RθJC(top) Junction-to-case (top) thermal resistance 32.2 38.9 °C/W RθJB Junction-to-board thermal resistance 6.5 7.4 °C/W ψJT Junction-to-top characterization parameter 2.5 3.8 °C/W ψJB Junction-to-board characterization parameter 6.5 7.4 °C/W RθJC(bot) Junction-to-case (bottom) thermal resistance 2.8 1.5 °C/W |
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