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VPX3225E Datasheet(PDF) 8 Page - Micronas |
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VPX3225E Datasheet(HTML) 8 Page - Micronas |
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8 / 92 page  ADVANCE INFORMATION VPX 322xE MICRONAS INTERMETALL 8 2. Functional Description The following sections provide an overview of the differ- ent functional blocks within the VPX. Most of them are controlled by the Fast Processor (‘FP’) embedded in the decoder. For controlling, there are two classes of regis- ters: I2C registers (directly addressable via I2C bus) and FP-RAM registers (RAM memory of the FP; indirectly addressable via I2C bus). For further information, see section 2.15.1. 2.1. Analog Front-End This block provides the analog interfaces to all video in- puts and mainly carries out analog-to-digital conversion for the following digital video processing. A block dia- gram is given in Fig. 2–1. Clamping, AGC, and clock DCO are digitally controlled. The control loops are closed by the embedded proces- sor. 2.1.1. Input Selector Up to four analog inputs can be connected. Three inputs (VIN1–3) are for input of composite video or S-VHS luma signal. These inputs are clamped to the sync back porch and are amplified by a variable gain amplifier. Two in- puts, one dedicated (CIN) and one shared (VIN1), are for connection of S-VHS carrier-chrominance signal. The chrominance input is internally biased and has a fixed gain amplifier. 2.1.2. Clamping The composite video input signals are AC coupled to the IC. The clamping voltage is stored on the coupling ca- pacitors and is generated by digitally controlled current sources. The clamping level is the back porch of the vid- eo signal. S-VHS chroma is AC coupled. The input pin is internally biased to the center of the ADC input range. 2.1.3. Automatic Gain Control A digitally working automatic gain control adjusts the magnitude of the selected baseband by +6/–4.5 dB in 64 logarithmic steps to the optimal range of the ADC. 2.1.4. Analog-to-Digital Converters Two ADCs are provided to digitize the input signals. Each converter runs with 20.25 MHz and has 8-bit reso- lution. An integrated bandgap circuit generates the re- quired reference voltages for the converters. The two ADCs are of a 2-stage subranging type. 2.1.5. ADC Range The ADC input range for the various input signals and the digital representation is given in Table 2–1 and Fig. 2–2. The corresponding output signal levels of the VPX 32xx are also shown. 2.1.6. Digitally Controlled Clock Oscillator The clock generation is also a part of the analog front end. The crystal oscillator is controlled digitally by the FP; the clock frequency can be adjusted within ±150 ppm. Fig. 2–1: Analog front-end input mux CVBS/Y CVBS/Y CVBS/Y/C Chroma VIN3 VIN2 VIN1 CIN clamp bias reference generation gain frequency ADC ADC DCVO ±150 ppm digital CVBS or Luma digital Chroma system clocks 20.25 MHz AGC +6/–4.5 dB |
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