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ADAU1451WBCPZ Datasheet(PDF) 3 Page - Analog Devices |
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ADAU1451WBCPZ Datasheet(HTML) 3 Page - Analog Devices |
3 / 180 page Data Sheet ADAU1452/ADAU1451/ADAU1450 REVISION HISTORY 7/14—Rev. B to Rev. C Changes to SCL_M/SCLK_M/MP2 Pin Description, Table 23.............................................................................................19 Change to PLL Lock Register Section ..........................................96 Changes to Ordering Guide.........................................................180 5/14—Rev. A to Rev. B Reorganized Layout ...........................................................Universal Added ADAU1452 and ADAU1451 .................................Universal Changes to Features Section ............................................................1 Moved Revision History Section.....................................................3 Changes to General Description Section .......................................4 Added Differences Between the ADAU1452, ADAU1451, and ADAU1450 Section and Table 1, Renumbered Sequentially .......4 Added Functional Block Diagram—ADAU1450 Section and Figure 2, Renumbered Sequentially................................................5 Changes to Table 2 ............................................................................6 Changes to Table 3 ............................................................................7 Changes to Table 6 ............................................................................9 Changes to Maximum Power Dissipation Section, Table 19, and Table 20 .....................................................................................17 Added Table 21 and Table 22.........................................................17 Changes to Figure 12 and Table 23 ...............................................18 Changes to Overview Section........................................................22 Change to Clocking Overview Section and Power-Up Sequence Section.............................................................................24 Changes to Setting the Master Clock and PLL Mode Section ..27 Changes to Example PLL Settings Section and Table 25 ...........28 Changed PLL Loop Filter Section to PLL Filter Section............29 Changes to PLL Filter Section, Figure 17 Caption, and Table 26.............................................................................................29 Changes to Clock Generators Section..........................................30 Changes to Master Clock Output Section ...................................31 Changes to I2C Slave Port Section.................................................35 Changes to Audio Signal Routing Section...................................43 Changes to Serial Audio Inputs to DSP Core Section................44 Changes to Asynchronous Sample Rate Converter Input Routing Section ...............................................................................49 Change to Serial Input Ports Section............................................61 Changes to Asynchronous Sample Rate Converters Section ....68 Changes to S/PDIF Interface Section and S/PDIF Receiver Section ..............................................................................................69 Changes to Auxiliary Output Mode Section ...............................70 Change to Digital PDM Microphone Interface Section ............71 Changes to SigmaDSP Core Section.............................................76 Changes to Soft Reset Function Section ......................................81 Changes to Random Access Memory Section.............................83 Added Table 62 and Table 63.........................................................83 Changes to Table 84 ......................................................................109 Changed PLL Loop Filter Section to PLL Filter Section..........176 Change to EOS/ESD Protection Section....................................177 Change to PCB Manufacturing Guidelines Section.................179 Changes to Ordering Guide.........................................................180 1/14—Rev. 0 to Rev. A Changed S/PDIF Transceiver and Receiver Maximum Audio Sample Rate from 192 kHz to 96 kHz; Table 9 and Table 10.......9 10/13—Revision 0: Initial Version Rev. C | Page 3 of 180 |
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